forked from OSchip/llvm-project
R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary
These are really the same address space in hardware. The only difference is that CONSTANT_ADDRESS uses a special cache for faster access. When we are unable to use the constant kcache for some reason (e.g. smaller types or lack of indirect addressing) then the instruction selector must use GLOBAL_ADDRESS loads instead. llvm-svn: 187006
This commit is contained in:
Tom Stellard
parent
2815782831
commit
8cb0e47c9e
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@ -620,6 +620,13 @@ bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
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}
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bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
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if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
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const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
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if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
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N->getMemoryVT().bitsLT(MVT::i32)) {
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return true;
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}
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}
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return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
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}
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@ -1418,16 +1418,6 @@ def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1,
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[(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
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>;
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//===----------------------------------------------------------------------===//
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// Constant Loads
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// XXX: We are currently storing all constants in the global address space.
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//===----------------------------------------------------------------------===//
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def CONSTANT_LOAD_eg : VTX_READ_32_eg <1,
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[(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
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>;
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} // End Predicates = [isEG]
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//===----------------------------------------------------------------------===//
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@ -1883,15 +1873,6 @@ def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1,
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[(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))]
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>;
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//===----------------------------------------------------------------------===//
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// Constant Loads
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// XXX: We are currently storing all constants in the global address space.
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//===----------------------------------------------------------------------===//
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def CONSTANT_LOAD_cm : VTX_READ_32_cm <1,
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[(set i32:$dst_gpr, (constant_load ADDRVTX_READ:$src_gpr))]
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>;
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} // End isCayman
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//===----------------------------------------------------------------------===//
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@ -2,6 +2,10 @@
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
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;===------------------------------------------------------------------------===;
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; GLOBAL ADDRESS SPACE
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;===------------------------------------------------------------------------===;
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; Load an i8 value from the global address space.
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; R600-CHECK: @load_i8
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; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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@ -100,31 +104,6 @@ entry:
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ret void
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}
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; Load an i32 value from the constant address space.
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; R600-CHECK: @load_const_addrspace_i32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_const_addrspace_i32
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; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}}
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define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) {
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entry:
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%0 = load i32 addrspace(2)* %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; Load a f32 value from the constant address space.
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; R600-CHECK: @load_const_addrspace_f32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_const_addrspace_f32
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; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}}
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define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
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%1 = load float addrspace(2)* %in
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store float %1, float addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @load_i64
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; R600-CHECK: RAT
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; R600-CHECK: RAT
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@ -166,3 +145,121 @@ entry:
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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;===------------------------------------------------------------------------===;
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; CONSTANT ADDRESS SPACE
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;===------------------------------------------------------------------------===;
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; Load a sign-extended i8 value
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; R600-CHECK: @load_const_i8_sext
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; R600-CHECK: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 24
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 24
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; SI-CHECK: @load_const_i8_sext
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; SI-CHECK: BUFFER_LOAD_SBYTE VGPR{{[0-9]+}},
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define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
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entry:
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%0 = load i8 addrspace(2)* %in
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%1 = sext i8 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an aligned i8 value
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; R600-CHECK: @load_const_i8_aligned
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; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i8_aligned
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; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}},
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define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
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entry:
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%0 = load i8 addrspace(2)* %in
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%1 = zext i8 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an un-aligned i8 value
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; R600-CHECK: @load_const_i8_unaligned
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; R600-CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i8_unaligned
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; SI-CHECK: BUFFER_LOAD_UBYTE VGPR{{[0-9]+}},
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define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) {
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entry:
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%0 = getelementptr i8 addrspace(2)* %in, i32 1
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%1 = load i8 addrspace(2)* %0
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%2 = zext i8 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; Load a sign-extended i16 value
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; R600-CHECK: @load_const_i16_sext
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; R600-CHECK: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]]
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; R600-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], [[DST]]
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; R600-CHECK: 16
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; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]]
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; R600-CHECK: 16
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; SI-CHECK: @load_const_i16_sext
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; SI-CHECK: BUFFER_LOAD_SSHORT
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define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
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entry:
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%0 = load i16 addrspace(2)* %in
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%1 = sext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an aligned i16 value
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; R600-CHECK: @load_const_i16_aligned
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; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i16_aligned
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
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entry:
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%0 = load i16 addrspace(2)* %in
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%1 = zext i16 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Load an un-aligned i16 value
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; R600-CHECK: @load_const_i16_unaligned
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; R600-CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
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; SI-CHECK: @load_const_i16_unaligned
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; SI-CHECK: BUFFER_LOAD_USHORT
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define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) {
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entry:
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%0 = getelementptr i16 addrspace(2)* %in, i32 1
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%1 = load i16 addrspace(2)* %0
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%2 = zext i16 %1 to i32
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store i32 %2, i32 addrspace(1)* %out
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ret void
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}
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; Load an i32 value from the constant address space.
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; R600-CHECK: @load_const_addrspace_i32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_const_addrspace_i32
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; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}}
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define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) {
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entry:
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%0 = load i32 addrspace(2)* %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; Load a f32 value from the constant address space.
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; R600-CHECK: @load_const_addrspace_f32
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; R600-CHECK: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
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; SI-CHECK: @load_const_addrspace_f32
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; SI-CHECK: S_LOAD_DWORD SGPR{{[0-9]+}}
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define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) {
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%1 = load float addrspace(2)* %in
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store float %1, float addrspace(1)* %out
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ret void
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}
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