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[InstSimplify] allow integer vector types to use computeKnownBits 

Note that the non-splat lshr+lshr test folded, but that does not
work in general. Something is missing or wrong in computeKnownBits
as the non-splat shl+shl test still shows.

llvm-svn: 288005
This commit is contained in:
Sanjay Patel 2016-11-27 21:07:28 +00:00
parent 4fab487265
commit 8ca30ab0c5
3 changed files with 10 additions and 22 deletions
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4
llvm/lib/Analysis/InstructionSimplify.cpp
View File

@ -4380,13 +4380,13 @@ Value *llvm::SimplifyInstruction(Instruction *I, const DataLayout &DL,
// In general, it is possible for computeKnownBits to determine all bits in a
// value even when the operands are not all constants.
if (!Result && I->getType()->isIntegerTy()) {
if (!Result && I->getType()->isIntOrIntVectorTy()) {
unsigned BitWidth = I->getType()->getScalarSizeInBits();
APInt KnownZero(BitWidth, 0);
APInt KnownOne(BitWidth, 0);
computeKnownBits(I, KnownZero, KnownOne, DL, /*Depth*/0, AC, I, DT);
if ((KnownZero | KnownOne).isAllOnesValue())
Result = ConstantInt::get(I->getContext(), KnownOne);
Result = ConstantInt::get(I->getType(), KnownOne);
}
/// If called on unreachable code, the above logic may report that the

10
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
View File

@ -580,13 +580,13 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
// Check for (X << c1) << c2 and (X >> c1) >> c2
if (I.getOpcode() == ShiftOp->getOpcode()) {
uint32_t AmtSum = ShiftAmt1+ShiftAmt2; // Fold into one big shift.
// If this is oversized composite shift, then unsigned shifts get 0, ashr
// saturates.
uint32_t AmtSum = ShiftAmt1 + ShiftAmt2; // Fold into one big shift.
// If this is an oversized composite shift, then unsigned shifts become
// zero (handled in InstSimplify) and ashr saturates.
if (AmtSum >= TypeBits) {
if (I.getOpcode() != Instruction::AShr)
return replaceInstUsesWith(I, Constant::getNullValue(I.getType()));
AmtSum = TypeBits-1; // Saturate to 31 for i32 ashr.
return nullptr;
AmtSum = TypeBits - 1; // Saturate to 31 for i32 ashr.
}
return BinaryOperator::Create(I.getOpcode(), X,

18
llvm/test/Analysis/ValueTracking/knownzero-shift.ll
View File

@ -24,13 +24,9 @@ define i32 @shl_shl(i32 %A) {
ret i32 %C
}
; FIXME
define <2 x i33> @shl_shl_splat_vec(<2 x i33> %A) {
; CHECK-LABEL: @shl_shl_splat_vec(
; CHECK-NEXT: [[B:%.*]] = shl <2 x i33> %A, <i33 5, i33 5>
; CHECK-NEXT: [[C:%.*]] = shl <2 x i33> [[B]], <i33 28, i33 28>
; CHECK-NEXT: ret <2 x i33> [[C]]
; CHECK-NEXT: ret <2 x i33> zeroinitializer
;
%B = shl <2 x i33> %A, <i33 5, i33 5>
%C = shl <2 x i33> %B, <i33 28, i33 28>
@ -59,26 +55,18 @@ define i232 @lshr_lshr(i232 %A) {
ret i232 %C
}
; FIXME
define <2 x i32> @lshr_lshr_splat_vec(<2 x i32> %A) {
; CHECK-LABEL: @lshr_lshr_splat_vec(
; CHECK-NEXT: [[B:%.*]] = lshr <2 x i32> %A, <i32 28, i32 28>
; CHECK-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], <i32 4, i32 4>
; CHECK-NEXT: ret <2 x i32> [[C]]
; CHECK-NEXT: ret <2 x i32> zeroinitializer
;
%B = lshr <2 x i32> %A, <i32 28, i32 28>
%C = lshr <2 x i32> %B, <i32 4, i32 4>
ret <2 x i32> %C
}
; FIXME
define <2 x i32> @lshr_lshr_vec(<2 x i32> %A) {
; CHECK-LABEL: @lshr_lshr_vec(
; CHECK-NEXT: [[B:%.*]] = lshr <2 x i32> %A, <i32 29, i32 28>
; CHECK-NEXT: [[C:%.*]] = lshr <2 x i32> [[B]], <i32 4, i32 5>
; CHECK-NEXT: ret <2 x i32> [[C]]
; CHECK-NEXT: ret <2 x i32> zeroinitializer
;
%B = lshr <2 x i32> %A, <i32 29, i32 28>
%C = lshr <2 x i32> %B, <i32 4, i32 5>