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Add FSGSBASE intrinsics to x86 intrinsic headers. 

llvm-svn: 221130
This commit is contained in:
Craig Topper 2014-11-03 06:51:41 +00:00
parent 72a643dc8f
commit 8c7f251e98
6 changed files with 142 additions and 15 deletions
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10
clang/include/clang/Basic/BuiltinsX86.def
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@ -625,6 +625,16 @@ BUILTIN(__builtin_ia32_rdrand16_step, "UiUs*", "")
BUILTIN(__builtin_ia32_rdrand32_step, "UiUi*", "")
BUILTIN(__builtin_ia32_rdrand64_step, "UiULLi*", "")
// FSGSBASE
BUILTIN(__builtin_ia32_rdfsbase32, "Ui", "")
BUILTIN(__builtin_ia32_rdfsbase64, "ULLi", "")
BUILTIN(__builtin_ia32_rdgsbase32, "Ui", "")
BUILTIN(__builtin_ia32_rdgsbase64, "ULLi", "")
BUILTIN(__builtin_ia32_wrfsbase32, "vUi", "")
BUILTIN(__builtin_ia32_wrfsbase64, "vULLi", "")
BUILTIN(__builtin_ia32_wrgsbase32, "vUi", "")
BUILTIN(__builtin_ia32_wrgsbase64, "vULLi", "")
// ADX
BUILTIN(__builtin_ia32_addcarryx_u32, "UcUcUiUiUi*", "")
BUILTIN(__builtin_ia32_addcarryx_u64, "UcUcULLiULLiULLi*", "")

2
clang/include/clang/Driver/Options.td
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@ -1134,6 +1134,7 @@ def mno_avx512vl : Flag<["-"], "mno-avx512vl">, Group<m_x86_Features_Group>;
def mno_pclmul : Flag<["-"], "mno-pclmul">, Group<m_x86_Features_Group>;
def mno_lzcnt : Flag<["-"], "mno-lzcnt">, Group<m_x86_Features_Group>;
def mno_rdrnd : Flag<["-"], "mno-rdrnd">, Group<m_x86_Features_Group>;
def mno_fsgsbase : Flag<["-"], "mno-fsgsbase">, Group<m_x86_Features_Group>;
def mno_bmi : Flag<["-"], "mno-bmi">, Group<m_x86_Features_Group>;
def mno_bmi2 : Flag<["-"], "mno-bmi2">, Group<m_x86_Features_Group>;
def mno_popcnt : Flag<["-"], "mno-popcnt">, Group<m_x86_Features_Group>;
@ -1243,6 +1244,7 @@ def mavx512vl : Flag<["-"], "mavx512vl">, Group<m_x86_Features_Group>;
def mpclmul : Flag<["-"], "mpclmul">, Group<m_x86_Features_Group>;
def mlzcnt : Flag<["-"], "mlzcnt">, Group<m_x86_Features_Group>;
def mrdrnd : Flag<["-"], "mrdrnd">, Group<m_x86_Features_Group>;
def mfsgsbase : Flag<["-"], "mfsgsbase">, Group<m_x86_Features_Group>;
def mbmi : Flag<["-"], "mbmi">, Group<m_x86_Features_Group>;
def mbmi2 : Flag<["-"], "mbmi2">, Group<m_x86_Features_Group>;
def mpopcnt : Flag<["-"], "mpopcnt">, Group<m_x86_Features_Group>;

31
clang/lib/Basic/Targets.cpp
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@ -1709,6 +1709,7 @@ class X86TargetInfo : public TargetInfo {
bool HasPCLMUL;
bool HasLZCNT;
bool HasRDRND;
bool HasFSGSBASE;
bool HasBMI;
bool HasBMI2;
bool HasPOPCNT;
@ -1886,12 +1887,12 @@ public:
X86TargetInfo(const llvm::Triple &Triple)
: TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasADX(false),
HasTBM(false), HasFMA(false), HasF16C(false), HasAVX512CD(false),
HasAVX512ER(false), HasAVX512PF(false), HasAVX512DQ(false),
HasAVX512BW(false), HasAVX512VL(false), HasSHA(false), HasCX16(false),
CPU(CK_Generic), FPMath(FP_Default) {
HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
BigEndian = false;
LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
}
@ -2193,6 +2194,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
setFeatureEnabledImpl(Features, "pclmul", true);
setFeatureEnabledImpl(Features, "rdrnd", true);
setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "fsgsbase", true);
break;
case CK_CoreAVX2:
setFeatureEnabledImpl(Features, "avx2", true);
@ -2201,6 +2203,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "rdrnd", true);
setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "fsgsbase", true);
setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
@ -2214,6 +2217,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "rdrnd", true);
setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "fsgsbase", true);
setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
@ -2232,6 +2236,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "rdrnd", true);
setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "fsgsbase", true);
setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
@ -2250,6 +2255,7 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "rdrnd", true);
setFeatureEnabledImpl(Features, "f16c", true);
setFeatureEnabledImpl(Features, "fsgsbase", true);
setFeatureEnabledImpl(Features, "bmi", true);
setFeatureEnabledImpl(Features, "bmi2", true);
setFeatureEnabledImpl(Features, "rtm", true);
@ -2329,8 +2335,10 @@ void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
setFeatureEnabledImpl(Features, "avx2", true);
setFeatureEnabledImpl(Features, "bmi2", true);
// FALLTHROUGH
case CK_BDVER2:
case CK_BDVER3:
setFeatureEnabledImpl(Features, "fsgsbase", true);
// FALLTHROUGH
case CK_BDVER2:
setFeatureEnabledImpl(Features, "xop", true);
setFeatureEnabledImpl(Features, "lzcnt", true);
setFeatureEnabledImpl(Features, "aes", true);
@ -2552,6 +2560,11 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
continue;
}
if (Feature == "fsgsbase") {
HasFSGSBASE = true;
continue;
}
if (Feature == "bmi") {
HasBMI = true;
continue;
@ -2889,6 +2902,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasRDRND)
Builder.defineMacro("__RDRND__");
if (HasFSGSBASE)
Builder.defineMacro("__FSGSBASE__");
if (HasBMI)
Builder.defineMacro("__BMI__");
@ -3037,6 +3053,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("tbm", HasTBM)
.Case("lzcnt", HasLZCNT)
.Case("rdrnd", HasRDRND)
.Case("fsgsbase", HasFSGSBASE)
.Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
.Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
.Case("mmx", MMX3DNowLevel >= MMX)

8
clang/lib/Headers/Intrin.h
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@ -410,10 +410,6 @@ char _InterlockedXor8_np(char volatile *_Value, char _Mask);
static __inline__
__int64 _mul128(__int64 _Multiplier, __int64 _Multiplicand,
__int64 *_HighProduct);
unsigned int __cdecl _readfsbase_u32(void);
unsigned __int64 __cdecl _readfsbase_u64(void);
unsigned int __cdecl _readgsbase_u32(void);
unsigned __int64 __cdecl _readgsbase_u64(void);
unsigned __int64 _rorx_u64(unsigned __int64, const unsigned int);
__int64 _sarx_i64(__int64, unsigned int);
#if __STDC_HOSTED__
@ -424,10 +420,6 @@ unsigned __int64 shrx_u64(unsigned __int64, unsigned int);
unsigned __int64 _umul128(unsigned __int64 _Multiplier,
unsigned __int64 _Multiplicand,
unsigned __int64 *_HighProduct);
void __cdecl _writefsbase_u32(unsigned int);
void _cdecl _writefsbase_u64(unsigned __int64);
void __cdecl _writegsbase_u32(unsigned int);
void __cdecl _writegsbase_u64(unsigned __int64);
void __cdecl _xrstor64(void const *, unsigned __int64);
void __cdecl _xsave64(void *, unsigned __int64);
void __cdecl _xsaveopt64(void *, unsigned __int64);

52
clang/lib/Headers/immintrin.h
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@ -118,6 +118,58 @@ _rdrand64_step(unsigned long long *__p)
#endif
#endif /* __RDRND__ */
#ifdef __FSGSBASE__
#ifdef __x86_64__
static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
_readfsbase_u32(void)
{
return __builtin_ia32_rdfsbase32();
}
static __inline__ unsigned long long __attribute__((__always_inline__, __nodebug__))
_readfsbase_u64(void)
{
return __builtin_ia32_rdfsbase64();
}
static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
_readgsbase_u32(void)
{
return __builtin_ia32_rdgsbase32();
}
static __inline__ unsigned long long __attribute__((__always_inline__, __nodebug__))
_readgsbase_u64(void)
{
return __builtin_ia32_rdgsbase64();
}
static __inline__ void __attribute__((__always_inline__, __nodebug__))
_writefsbase_u32(unsigned int __V)
{
return __builtin_ia32_wrfsbase32(__V);
}
static __inline__ void __attribute__((__always_inline__, __nodebug__))
_writefsbase_u64(unsigned long long __V)
{
return __builtin_ia32_wrfsbase64(__V);
}
static __inline__ void __attribute__((__always_inline__, __nodebug__))
_writegsbase_u32(unsigned int __V)
{
return __builtin_ia32_wrgsbase32(__V);
}
static __inline__ void __attribute__((__always_inline__, __nodebug__))
_writegsbase_u64(unsigned long long __V)
{
return __builtin_ia32_wrgsbase64(__V);
}
#endif
#endif /* __FSGSBASE__ */
#ifdef __RTM__
#include <rtmintrin.h>
#endif

54
clang/test/CodeGen/fsgsbase-builtins.c Normal file
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@ -0,0 +1,54 @@
// RUN: %clang_cc1 %s -O3 -triple=x86_64-apple-darwin -target-feature +fsgsbase -emit-llvm -o - | FileCheck %s
// Don't include mm_malloc.h, it's system specific.
#define __MM_MALLOC_H
#include <x86intrin.h>
unsigned int test_readfsbase_u32()
{
// CHECK: @llvm.x86.rdfsbase.32
return _readfsbase_u32();
}
unsigned long long test_readfsbase_u64()
{
// CHECK: @llvm.x86.rdfsbase.64
return _readfsbase_u64();
}
unsigned int test_readgsbase_u32()
{
// CHECK: @llvm.x86.rdgsbase.32
return _readgsbase_u32();
}
unsigned long long test_readgsbase_u64()
{
// CHECK: @llvm.x86.rdgsbase.64
return _readgsbase_u64();
}
void test_writefsbase_u32(unsigned int __X)
{
// CHECK: @llvm.x86.wrfsbase.32
_writefsbase_u32(__X);
}
void test_writefsbase_u64(unsigned long long __X)
{
// CHECK: @llvm.x86.wrfsbase.64
_writefsbase_u64(__X);
}
void test_writegsbase_u32(unsigned int __X)
{
// CHECK: @llvm.x86.wrgsbase.32
_writegsbase_u32(__X);
}
void test_writegsbase_u64(unsigned long long __X)
{
// CHECK: @llvm.x86.wrgsbase.64
_writegsbase_u64(__X);
}