forked from OSchip/llvm-project
[Hexagon] Updating constant set to simpler versions.
llvm-svn: 231699
This commit is contained in:
Colin LeMahieu
parent
294fa7aa9d
commit
8c4dfaa13b
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@ -332,73 +332,6 @@ static unsigned doesIntrinsicReturnPredicate(unsigned ID)
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}
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}
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}
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}
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static bool OffsetFitsS11(EVT MemType, int64_t Offset) {
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if (MemType == MVT::i64 && isShiftedInt<11,3>(Offset)) {
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return true;
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}
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if (MemType == MVT::i32 && isShiftedInt<11,2>(Offset)) {
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return true;
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}
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if (MemType == MVT::i16 && isShiftedInt<11,1>(Offset)) {
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return true;
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}
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if (MemType == MVT::i8 && isInt<11>(Offset)) {
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return true;
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}
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return false;
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}
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//
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// Try to lower loads of GlobalAdresses into base+offset loads. Custom
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// lowering for GlobalAddress nodes has already turned it into a
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// CONST32.
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//
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SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl) {
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SDValue Chain = LD->getChain();
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SDNode* Const32 = LD->getBasePtr().getNode();
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unsigned Opcode = 0;
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if (Const32->getOpcode() == HexagonISD::CONST32 &&
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ISD::isNormalLoad(LD)) {
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SDValue Base = Const32->getOperand(0);
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EVT LoadedVT = LD->getMemoryVT();
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int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
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if (Offset != 0 && OffsetFitsS11(LoadedVT, Offset)) {
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MVT PointerTy = getTargetLowering()->getPointerTy();
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const GlobalValue* GV =
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cast<GlobalAddressSDNode>(Base)->getGlobal();
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SDValue TargAddr =
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CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
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SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
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dl, PointerTy,
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TargAddr);
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// Figure out base + offset opcode
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if (LoadedVT == MVT::i64) Opcode = Hexagon::L2_loadrd_io;
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else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;
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else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;
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else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;
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else llvm_unreachable("unknown memory type");
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// Build indexed load.
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SDValue TargetConstOff = CurDAG->getTargetConstant(Offset, PointerTy);
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SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
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LD->getValueType(0),
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MVT::Other,
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SDValue(NewBase,0),
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TargetConstOff,
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Chain);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = LD->getMemOperand();
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cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
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ReplaceUses(LD, Result);
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return Result;
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}
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}
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return SelectCode(LD);
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}
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SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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unsigned Opcode,
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unsigned Opcode,
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@ -649,7 +582,7 @@ SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
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if (AM != ISD::UNINDEXED) {
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if (AM != ISD::UNINDEXED) {
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result = SelectIndexedLoad(LD, dl);
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result = SelectIndexedLoad(LD, dl);
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} else {
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} else {
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result = SelectBaseOffsetLoad(LD, dl);
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result = SelectCode(LD);
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}
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}
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return result;
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return result;
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@ -725,60 +658,6 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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}
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}
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SDNode *HexagonDAGToDAGISel::SelectBaseOffsetStore(StoreSDNode *ST,
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SDLoc dl) {
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SDValue Chain = ST->getChain();
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SDNode* Const32 = ST->getBasePtr().getNode();
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SDValue Value = ST->getValue();
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unsigned Opcode = 0;
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// Try to lower stores of GlobalAdresses into indexed stores. Custom
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// lowering for GlobalAddress nodes has already turned it into a
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// CONST32. Avoid truncating stores for the moment. Post-inc stores
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// do the same. Don't think there's a reason for it, so will file a
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// bug to fix.
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if ((Const32->getOpcode() == HexagonISD::CONST32) &&
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!(Value.getValueType() == MVT::i64 && ST->isTruncatingStore())) {
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SDValue Base = Const32->getOperand(0);
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if (Base.getOpcode() == ISD::TargetGlobalAddress) {
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EVT StoredVT = ST->getMemoryVT();
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int64_t Offset = cast<GlobalAddressSDNode>(Base)->getOffset();
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if (Offset != 0 && OffsetFitsS11(StoredVT, Offset)) {
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MVT PointerTy = getTargetLowering()->getPointerTy();
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const GlobalValue* GV =
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cast<GlobalAddressSDNode>(Base)->getGlobal();
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SDValue TargAddr =
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CurDAG->getTargetGlobalAddress(GV, dl, PointerTy, 0);
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SDNode* NewBase = CurDAG->getMachineNode(Hexagon::CONST32_set,
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dl, PointerTy,
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TargAddr);
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// Figure out base + offset opcode
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if (StoredVT == MVT::i64) Opcode = Hexagon::S2_storerd_io;
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else if (StoredVT == MVT::i32) Opcode = Hexagon::S2_storeri_io;
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else if (StoredVT == MVT::i16) Opcode = Hexagon::S2_storerh_io;
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else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_io;
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else llvm_unreachable("unknown memory type");
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SDValue Ops[] = {SDValue(NewBase,0),
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CurDAG->getTargetConstant(Offset,PointerTy),
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Value, Chain};
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// build indexed store
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SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
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MVT::Other, Ops);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = ST->getMemOperand();
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cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1);
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ReplaceUses(ST, Result);
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return Result;
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}
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}
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}
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return SelectCode(ST);
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}
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SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
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SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
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SDLoc dl(N);
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SDLoc dl(N);
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StoreSDNode *ST = cast<StoreSDNode>(N);
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StoreSDNode *ST = cast<StoreSDNode>(N);
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@ -789,7 +668,7 @@ SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
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return SelectIndexedStore(ST, dl);
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return SelectIndexedStore(ST, dl);
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}
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}
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return SelectBaseOffsetStore(ST, dl);
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return SelectCode(ST);
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}
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}
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SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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@ -4805,31 +4805,19 @@ def CONST32 : CONSTLDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
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(load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
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(load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
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let isReMaterializable = 1, isMoveImm = 1 in
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let isReMaterializable = 1, isMoveImm = 1 in
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def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
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"$dst = CONST32(#$global)",
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[(set (i32 IntRegs:$dst),
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(HexagonCONST32 tglobaladdr:$global))]>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
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def CONST32_set_jt : CONSTLDInst<(outs IntRegs:$dst), (ins jumptablebase:$jt),
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"$dst = CONST32(#$jt)",
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"$dst = CONST32(#$jt)",
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[(set (i32 IntRegs:$dst),
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[(set (i32 IntRegs:$dst),
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(HexagonCONST32 tjumptable:$jt))]>;
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(HexagonCONST32 tjumptable:$jt))]>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
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"$dst = CONST32(#$global)",
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[(set (i32 IntRegs:$dst),
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(HexagonCONST32_GP tglobaladdr:$global))]>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
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def CONST32_Int_Real : CONSTLDInst<(outs IntRegs:$dst), (ins i32imm:$global),
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"$dst = CONST32(#$global)",
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"$dst = CONST32(#$global)",
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[(set (i32 IntRegs:$dst), imm:$global) ]>;
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[(set (i32 IntRegs:$dst), imm:$global) ]>;
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// Map BlockAddress lowering to CONST32_Int_Real
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// Map TLS addressses to a CONST32 instruction
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def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
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def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>;
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(CONST32_Int_Real tblockaddress:$addr)>;
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def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
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def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
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def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
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@ -1,4 +1,5 @@
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; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; XFAIL:
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)
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; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)
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; CHECK: memw(r29+#0) = r{{.}}
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; CHECK: memw(r29+#0) = r{{.}}
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; CHECK: memw(r29+#8) = r{{.}}
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; CHECK: memw(r29+#8) = r{{.}}
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