forked from OSchip/llvm-project
[NVPTX] Add add.cc/addc.cc/sub.cc/subc.cc for i64
PTX supports those instructions for i64 starting from 4.3. The patch also marks corresponding DAG nodes legal for both i32 and i64. Reviewed By: tra Differential Revision: https://reviews.llvm.org/D124698
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@ -487,6 +487,17 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
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setOperationAction(ISD::CTLZ, Ty, Legal);
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setOperationAction(ISD::CTLZ, Ty, Legal);
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}
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}
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setOperationAction(ISD::ADDC, MVT::i32, Legal);
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setOperationAction(ISD::ADDE, MVT::i32, Legal);
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setOperationAction(ISD::SUBC, MVT::i32, Legal);
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setOperationAction(ISD::SUBE, MVT::i32, Legal);
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if (STI.getPTXVersion() >= 43) {
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setOperationAction(ISD::ADDC, MVT::i64, Legal);
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setOperationAction(ISD::ADDE, MVT::i64, Legal);
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setOperationAction(ISD::SUBC, MVT::i64, Legal);
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setOperationAction(ISD::SUBE, MVT::i64, Legal);
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}
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setOperationAction(ISD::CTTZ, MVT::i16, Expand);
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setOperationAction(ISD::CTTZ, MVT::i16, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i64, Expand);
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setOperationAction(ISD::CTTZ, MVT::i64, Expand);
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@ -146,6 +146,7 @@ def True : Predicate<"true">;
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def hasPTX31 : Predicate<"Subtarget->getPTXVersion() >= 31">;
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def hasPTX31 : Predicate<"Subtarget->getPTXVersion() >= 31">;
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def hasPTX42 : Predicate<"Subtarget->getPTXVersion() >= 42">;
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def hasPTX42 : Predicate<"Subtarget->getPTXVersion() >= 42">;
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def hasPTX43 : Predicate<"Subtarget->getPTXVersion() >= 43">;
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def hasPTX60 : Predicate<"Subtarget->getPTXVersion() >= 60">;
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def hasPTX60 : Predicate<"Subtarget->getPTXVersion() >= 60">;
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def hasPTX61 : Predicate<"Subtarget->getPTXVersion() >= 61">;
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def hasPTX61 : Predicate<"Subtarget->getPTXVersion() >= 61">;
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def hasPTX63 : Predicate<"Subtarget->getPTXVersion() >= 63">;
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def hasPTX63 : Predicate<"Subtarget->getPTXVersion() >= 63">;
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@ -204,17 +205,29 @@ multiclass I3<string OpcStr, SDNode OpNode> {
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[(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
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[(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
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}
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}
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// Template for instructions which take 3 int32 args. The instructions are
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// Template for instructions which take 3 int args. The instructions are
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// named "<OpcStr>.s32" (e.g. "addc.cc.s32").
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// named "<OpcStr>.s32" (e.g. "addc.cc.s32").
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multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
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multiclass ADD_SUB_INT_CARRY<string OpcStr, SDNode OpNode> {
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def i32rr :
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let hasSideEffects = 1 in {
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NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
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def i32rr :
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!strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
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NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, Int32Regs:$b),
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[(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
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!strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
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def i32ri :
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[(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
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NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
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def i32ri :
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!strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
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NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a, i32imm:$b),
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[(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
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!strconcat(OpcStr, ".s32 \t$dst, $a, $b;"),
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[(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
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def i64rr :
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NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, Int64Regs:$b),
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!strconcat(OpcStr, ".s64 \t$dst, $a, $b;"),
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[(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>,
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Requires<[hasPTX43]>;
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def i64ri :
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NVPTXInst<(outs Int64Regs:$dst), (ins Int64Regs:$a, i64imm:$b),
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!strconcat(OpcStr, ".s64 \t$dst, $a, $b;"),
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[(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>,
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Requires<[hasPTX43]>;
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}
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}
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}
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// Template for instructions which take three fp64 or fp32 args. The
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// Template for instructions which take three fp64 or fp32 args. The
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@ -584,14 +597,13 @@ defm SUB_i1 : ADD_SUB_i1<sub>;
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defm ADD : I3<"add.s", add>;
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defm ADD : I3<"add.s", add>;
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defm SUB : I3<"sub.s", sub>;
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defm SUB : I3<"sub.s", sub>;
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// int32 addition and subtraction with carry-out.
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// in32 and int64 addition and subtraction with carry-out.
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// FIXME: PTX 4.3 adds a 64-bit add.cc (and maybe also 64-bit addc.cc?).
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defm ADDCC : ADD_SUB_INT_CARRY<"add.cc", addc>;
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defm ADDCC : ADD_SUB_INT_32<"add.cc", addc>;
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defm SUBCC : ADD_SUB_INT_CARRY<"sub.cc", subc>;
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defm SUBCC : ADD_SUB_INT_32<"sub.cc", subc>;
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// int32 addition and subtraction with carry-in and carry-out.
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// int32 and int64 addition and subtraction with carry-in and carry-out.
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defm ADDCCC : ADD_SUB_INT_32<"addc.cc", adde>;
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defm ADDCCC : ADD_SUB_INT_CARRY<"addc.cc", adde>;
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defm SUBCCC : ADD_SUB_INT_32<"subc.cc", sube>;
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defm SUBCCC : ADD_SUB_INT_CARRY<"subc.cc", sube>;
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defm MULT : I3<"mul.lo.s", mul>;
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defm MULT : I3<"mul.lo.s", mul>;
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@ -1,20 +0,0 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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define void @foo(i64 %a, i64 %add, i128* %retptr) {
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; CHECK: add.s64
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; CHECK: setp.lt.u64
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; CHECK: setp.lt.u64
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; CHECK: selp.u64
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; CHECK: selp.b64
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; CHECK: add.s64
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%t1 = sext i64 %a to i128
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%add2 = zext i64 %add to i128
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%val = add i128 %t1, %add2
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store i128 %val, i128* %retptr
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ret void
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}
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@ -0,0 +1,36 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefixes=COMMON,NOCARRY
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 -mattr=+ptx43 | FileCheck %s --check-prefixes=COMMON,CARRY
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; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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; COMMON-LABEL: test_add
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define i128 @test_add(i128 %a, i128 %b) {
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; NOCARRY: add.s64
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; NOCARRY-NEXT: setp.lt.u64
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; NOCARRY-NEXT: setp.lt.u64
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; NOCARRY-NEXT: selp.u64
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; NOCARRY-NEXT: selp.b64
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; NOCARRY-NEXT: add.s64
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; CARRY: add.cc.s64
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; CARRY-NEXT: addc.cc.s64
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%1 = add i128 %a, %b
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ret i128 %1
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}
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; COMMON-LABEL: test_sub
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define i128 @test_sub(i128 %a, i128 %b) {
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; NOCARRY: sub.s64
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; NOCARRY-NEXT: setp.lt.u64
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; NOCARRY-NEXT: selp.s64
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; NOCARRY-NEXT: add.s64
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; NOCARRY-NEXT: sub.s64
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; CARRY: sub.cc.s64
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; CARRY-NEXT: subc.cc.s64
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%1 = sub i128 %a, %b
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ret i128 %1
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}
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