From 8c389bd368134b34fd9c5004d5128b786ace4fa7 Mon Sep 17 00:00:00 2001 From: Krzysztof Parzyszek Date: Tue, 15 May 2018 16:13:52 +0000 Subject: [PATCH] [Hexagon] Remove unused flag from subtarget and (non)corresponding test llvm-svn: 332365 --- llvm/lib/Target/Hexagon/Hexagon.td | 1 - llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 5 ---- llvm/lib/Target/Hexagon/HexagonSubtarget.h | 2 -- .../Hexagon/doubleconvert-ieee-rnd-near.ll | 26 ------------------- 4 files changed, 34 deletions(-) delete mode 100644 llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 6fa90d9ce62b..fdd1e213199e 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -66,7 +66,6 @@ def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19", //===----------------------------------------------------------------------===// def UseMEMOPS : Predicate<"HST->useMemops()">; -def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; def UseHVX64B : Predicate<"HST->useHVX64BOps()">, AssemblerPredicate<"ExtensionHVX64B">; def UseHVX128B : Predicate<"HST->useHVX128BOps()">, diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 743fe39b8025..14e2bf83e2af 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -40,10 +40,6 @@ using namespace llvm; #include "HexagonGenSubtargetInfo.inc" -static cl::opt EnableIEEERndNear("enable-hexagon-ieee-rnd-near", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Generate non-chopped conversion from fp to int.")); - static cl::opt EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true)); @@ -114,7 +110,6 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { UseHVX64BOps = false; UseLongCalls = false; - ModeIEEERndNear = EnableIEEERndNear; UseBSBScheduling = hasV60TOps() && EnableBSBSched; ParseSubtargetFeatures(CPUString, FS); diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index 936971fbced5..800e3fe35eff 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -48,7 +48,6 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { bool UseHVX64BOps = false; bool UseHVX128BOps = false; - bool ModeIEEERndNear = false; bool UseLongCalls = false; bool UseMemops = false; @@ -162,7 +161,6 @@ public: bool useNewValueStores() const { return UseNewValueStores; } bool useSmallData() const { return UseSmallData; } - bool modeIEEERndNear() const { return ModeIEEERndNear; } bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; } bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } diff --git a/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll b/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll deleted file mode 100644 index ccc287c5f2bc..000000000000 --- a/llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-hexagon-ieee-rnd-near < %s | FileCheck %s -; Check that we generate conversion from double precision floating point -; to 32-bit int value in IEEE rounding to the nearest mode in V5. - -; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}}) - -define i32 @main() nounwind { -entry: - %retval = alloca i32, align 4 - %i = alloca i32, align 4 - %a = alloca double, align 8 - %b = alloca double, align 8 - %c = alloca double, align 8 - store i32 0, i32* %retval - store volatile double 1.540000e+01, double* %a, align 8 - store volatile double 9.100000e+00, double* %b, align 8 - %0 = load volatile double, double* %a, align 8 - %1 = load volatile double, double* %b, align 8 - %add = fadd double %0, %1 - store double %add, double* %c, align 8 - %2 = load double, double* %c, align 8 - %conv = fptosi double %2 to i32 - store i32 %conv, i32* %i, align 4 - %3 = load i32, i32* %i, align 4 - ret i32 %3 -}