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[Hexagon] Remove unused flag from subtarget and (non)corresponding test 

llvm-svn: 332365
This commit is contained in:
Krzysztof Parzyszek 2018-05-15 16:13:52 +00:00
parent f40eb03ce9
commit 8c389bd368
4 changed files with 0 additions and 34 deletions
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1
llvm/lib/Target/Hexagon/Hexagon.td
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@ -66,7 +66,6 @@ def FeatureReservedR19: SubtargetFeature<"reserved-r19", "ReservedR19",
//===----------------------------------------------------------------------===//
def UseMEMOPS : Predicate<"HST->useMemops()">;
def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">;
def UseHVX64B : Predicate<"HST->useHVX64BOps()">,
AssemblerPredicate<"ExtensionHVX64B">;
def UseHVX128B : Predicate<"HST->useHVX128BOps()">,

5
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
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@ -40,10 +40,6 @@ using namespace llvm;
#include "HexagonGenSubtargetInfo.inc"
static cl::opt<bool> EnableIEEERndNear("enable-hexagon-ieee-rnd-near",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Generate non-chopped conversion from fp to int."));
static cl::opt<bool> EnableBSBSched("enable-bsb-sched",
cl::Hidden, cl::ZeroOrMore, cl::init(true));
@ -114,7 +110,6 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
UseHVX64BOps = false;
UseLongCalls = false;
ModeIEEERndNear = EnableIEEERndNear;
UseBSBScheduling = hasV60TOps() && EnableBSBSched;
ParseSubtargetFeatures(CPUString, FS);

2
llvm/lib/Target/Hexagon/HexagonSubtarget.h
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@ -48,7 +48,6 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo {
bool UseHVX64BOps = false;
bool UseHVX128BOps = false;
bool ModeIEEERndNear = false;
bool UseLongCalls = false;
bool UseMemops = false;
@ -162,7 +161,6 @@ public:
bool useNewValueStores() const { return UseNewValueStores; }
bool useSmallData() const { return UseSmallData; }
bool modeIEEERndNear() const { return ModeIEEERndNear; }
bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; }
bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; }
bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; }

26
llvm/test/CodeGen/Hexagon/doubleconvert-ieee-rnd-near.ll
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@ -1,26 +0,0 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-hexagon-ieee-rnd-near < %s | FileCheck %s
; Check that we generate conversion from double precision floating point
; to 32-bit int value in IEEE rounding to the nearest mode in V5.
; CHECK: r{{[0-9]+}} = convert_df2w(r{{[0-9]+}}:{{[0-9]+}})
define i32 @main() nounwind {
entry:
%retval = alloca i32, align 4
%i = alloca i32, align 4
%a = alloca double, align 8
%b = alloca double, align 8
%c = alloca double, align 8
store i32 0, i32* %retval
store volatile double 1.540000e+01, double* %a, align 8
store volatile double 9.100000e+00, double* %b, align 8
%0 = load volatile double, double* %a, align 8
%1 = load volatile double, double* %b, align 8
%add = fadd double %0, %1
store double %add, double* %c, align 8
%2 = load double, double* %c, align 8
%conv = fptosi double %2 to i32
store i32 %conv, i32* %i, align 4
%3 = load i32, i32* %i, align 4
ret i32 %3
}