forked from OSchip/llvm-project
[RISCV] MC layer support for the standard RV32A instruction set extension
llvm-svn: 317791
This commit is contained in:
Alex Bradbury
parent
89d31658e5
commit
8c345c5aa9
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@ -52,7 +52,8 @@ class RISCVAsmParser : public MCTargetAsmParser {
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#include "RISCVGenAsmMatcher.inc"
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OperandMatchResultTy parseImmediate(OperandVector &Operands);
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OperandMatchResultTy parseRegister(OperandVector &Operands);
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OperandMatchResultTy parseRegister(OperandVector &Operands,
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bool AllowParens = false);
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OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands);
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OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands);
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@ -431,9 +432,20 @@ bool RISCVAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
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return Error(StartLoc, "invalid register name");
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}
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OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands) {
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SMLoc S = getLoc();
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SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
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OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands,
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bool AllowParens) {
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SMLoc FirstS = getLoc();
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bool HadParens = false;
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AsmToken Buf[2];
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// If this a parenthesised register name is allowed, parse it atomically
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if (AllowParens && getLexer().is(AsmToken::LParen)) {
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size_t ReadCount = getLexer().peekTokens(Buf);
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if (ReadCount == 2 && Buf[1].getKind() == AsmToken::RParen) {
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HadParens = true;
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getParser().Lex(); // Eat '('
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}
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}
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switch (getLexer().getKind()) {
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default:
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@ -443,12 +455,25 @@ OperandMatchResultTy RISCVAsmParser::parseRegister(OperandVector &Operands) {
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unsigned RegNo = MatchRegisterName(Name);
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if (RegNo == 0) {
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RegNo = MatchRegisterAltName(Name);
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if (RegNo == 0)
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if (RegNo == 0) {
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if (HadParens)
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getLexer().UnLex(Buf[0]);
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return MatchOperand_NoMatch;
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}
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}
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if (HadParens)
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Operands.push_back(RISCVOperand::createToken("(", FirstS));
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SMLoc S = getLoc();
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SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
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getLexer().Lex();
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Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
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}
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if (HadParens) {
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getParser().Lex(); // Eat ')'
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Operands.push_back(RISCVOperand::createToken(")", getLoc()));
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}
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return MatchOperand_Success;
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}
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@ -555,7 +580,7 @@ RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
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/// If operand was parsed, returns false, else true.
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bool RISCVAsmParser::parseOperand(OperandVector &Operands) {
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// Attempt to parse token as register
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if (parseRegister(Operands) == MatchOperand_Success)
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if (parseRegister(Operands, true) == MatchOperand_Success)
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return false;
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// Attempt to parse token as an immediate
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@ -13,13 +13,20 @@ include "llvm/Target/Target.td"
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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def FeatureStdExtM
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: SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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AssemblerPredicate<"FeatureStdExtM">;
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def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
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"Implements RV64">;
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def FeatureStdExtA
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: SubtargetFeature<"a", "HasStdExtA", "true",
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"'A' (Atomic Instructions)">;
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def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
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AssemblerPredicate<"FeatureStdExtA">;
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def Feature64Bit
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: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
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def RV64 : HwMode<"+64bit">;
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def RV32 : HwMode<"-64bit">;
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@ -118,6 +118,24 @@ class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
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let Opcode = opcode.Value;
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}
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class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
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RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
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string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
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bits<5> rs2;
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bits<5> rs1;
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bits<5> rd;
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let Inst{31-27} = funct5;
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let Inst{26} = aq;
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let Inst{25} = rl;
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let Inst{24-20} = rs2;
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let Inst{19-15} = rs1;
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let Inst{14-12} = funct3;
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let Inst{11-7} = rd;
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let Opcode = opcode.Value;
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}
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class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
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string opcodestr, string argstr>
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: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
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@ -405,3 +405,4 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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//===----------------------------------------------------------------------===//
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include "RISCVInstrInfoM.td"
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include "RISCVInstrInfoA.td"
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@ -0,0 +1,63 @@
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//===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'A', Atomic
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// Instructions extension.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs1),
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opcodestr, "$rd, (${rs1})"> {
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let rs2 = 0;
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}
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multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
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def "" : LR_r<0, 0, funct3, opcodestr>;
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def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
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def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
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class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
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opcodestr, "$rd, $rs2, (${rs1})">;
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multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
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def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
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def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
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def _RL : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtA] in {
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defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
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defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
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defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
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defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
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defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
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defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
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defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
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defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
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defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
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defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
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defm AMOMAXU_W : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
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} // Predicates = [HasStdExtA]
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@ -30,7 +30,8 @@ class StringRef;
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class RISCVSubtarget : public RISCVGenSubtargetInfo {
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virtual void anchor();
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bool HasStdExtM;
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bool HasStdExtM = false;
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bool HasStdExtA = false;
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bool HasRV64 = false;
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unsigned XLen = 32;
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MVT XLenVT = MVT::i32;
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@ -68,6 +69,7 @@ public:
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return &TSInfo;
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}
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bool hasStdExtM() const { return HasStdExtM; }
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bool hasStdExtA() const { return HasStdExtA; }
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bool is64Bit() const { return HasRV64; }
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MVT getXLenVT() const { return XLenVT; }
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unsigned getXLen() const { return XLen; }
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@ -0,0 +1,14 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
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# Final operand must have parentheses
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amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
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amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction
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lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
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# Only .aq, .rl, and .aqrl suffixes are valid
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amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
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# lr only takes two operands
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lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
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@ -0,0 +1,146 @@
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+a < %s \
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# RUN: | llvm-objdump -mattr=+a -d - | FileCheck -check-prefix=CHECK-INST %s
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# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+a < %s \
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# RUN: | llvm-objdump -mattr=+a -d - | FileCheck -check-prefix=CHECK-INST %s
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# CHECK-INST: lr.w t0, (t1)
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# CHECK: encoding: [0xaf,0x22,0x03,0x10]
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lr.w t0, (t1)
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# CHECK-INST: lr.w.aq t1, (t2)
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# CHECK: encoding: [0x2f,0xa3,0x03,0x14]
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lr.w.aq t1, (t2)
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# CHECK-INST: lr.w.rl t2, (t3)
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# CHECK: encoding: [0xaf,0x23,0x0e,0x12]
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lr.w.rl t2, (t3)
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# CHECK-INST: lr.w.aqrl t3, (t4)
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# CHECK: encoding: [0x2f,0xae,0x0e,0x16]
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lr.w.aqrl t3, (t4)
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# CHECK-INST: sc.w t6, t5, (t4)
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# CHECK: encoding: [0xaf,0xaf,0xee,0x19]
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sc.w t6, t5, (t4)
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# CHECK-INST: sc.w.aq t5, t4, (t3)
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# CHECK: encoding: [0x2f,0x2f,0xde,0x1d]
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sc.w.aq t5, t4, (t3)
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# CHECK-INST: sc.w.rl t4, t3, (t2)
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# CHECK: encoding: [0xaf,0xae,0xc3,0x1b]
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sc.w.rl t4, t3, (t2)
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# CHECK-INST: sc.w.aqrl t3, t2, (t1)
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# CHECK: encoding: [0x2f,0x2e,0x73,0x1e]
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sc.w.aqrl t3, t2, (t1)
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# CHECK-INST: amoswap.w a4, ra, (s0)
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# CHECK: encoding: [0x2f,0x27,0x14,0x08]
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amoswap.w a4, ra, (s0)
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# CHECK-INST: amoadd.w a1, a2, (a3)
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# CHECK: encoding: [0xaf,0xa5,0xc6,0x00]
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amoadd.w a1, a2, (a3)
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# CHECK-INST: amoxor.w a2, a3, (a4)
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# CHECK: encoding: [0x2f,0x26,0xd7,0x20]
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amoxor.w a2, a3, (a4)
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# CHECK-INST: amoand.w a3, a4, (a5)
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# CHECK: encoding: [0xaf,0xa6,0xe7,0x60]
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amoand.w a3, a4, (a5)
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# CHECK-INST: amoor.w a4, a5, (a6)
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# CHECK: encoding: [0x2f,0x27,0xf8,0x40]
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amoor.w a4, a5, (a6)
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# CHECK-INST: amomin.w a5, a6, (a7)
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# CHECK: encoding: [0xaf,0xa7,0x08,0x81]
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amomin.w a5, a6, (a7)
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# CHECK-INST: amomax.w s7, s6, (s5)
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# CHECK: encoding: [0xaf,0xab,0x6a,0xa1]
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amomax.w s7, s6, (s5)
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# CHECK-INST: amominu.w s6, s5, (s4)
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# CHECK: encoding: [0x2f,0x2b,0x5a,0xc1]
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amominu.w s6, s5, (s4)
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# CHECK-INST: amomaxu.w s5, s4, (s3)
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# CHECK: encoding: [0xaf,0xaa,0x49,0xe1]
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amomaxu.w s5, s4, (s3)
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# CHECK-INST: amoswap.w.aq a4, ra, (s0)
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# CHECK: encoding: [0x2f,0x27,0x14,0x0c]
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amoswap.w.aq a4, ra, (s0)
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# CHECK-INST: amoadd.w.aq a1, a2, (a3)
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# CHECK: encoding: [0xaf,0xa5,0xc6,0x04]
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amoadd.w.aq a1, a2, (a3)
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# CHECK-INST: amoxor.w.aq a2, a3, (a4)
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# CHECK: encoding: [0x2f,0x26,0xd7,0x24]
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amoxor.w.aq a2, a3, (a4)
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# CHECK-INST: amoand.w.aq a3, a4, (a5)
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# CHECK: encoding: [0xaf,0xa6,0xe7,0x64]
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amoand.w.aq a3, a4, (a5)
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# CHECK-INST: amoor.w.aq a4, a5, (a6)
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# CHECK: encoding: [0x2f,0x27,0xf8,0x44]
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amoor.w.aq a4, a5, (a6)
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# CHECK-INST: amomin.w.aq a5, a6, (a7)
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# CHECK: encoding: [0xaf,0xa7,0x08,0x85]
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amomin.w.aq a5, a6, (a7)
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# CHECK-INST: amomax.w.aq s7, s6, (s5)
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# CHECK: encoding: [0xaf,0xab,0x6a,0xa5]
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amomax.w.aq s7, s6, (s5)
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# CHECK-INST: amominu.w.aq s6, s5, (s4)
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# CHECK: encoding: [0x2f,0x2b,0x5a,0xc5]
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amominu.w.aq s6, s5, (s4)
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# CHECK-INST: amomaxu.w.aq s5, s4, (s3)
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# CHECK: encoding: [0xaf,0xaa,0x49,0xe5]
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amomaxu.w.aq s5, s4, (s3)
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# CHECK-INST: amoswap.w.rl a4, ra, (s0)
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# CHECK: encoding: [0x2f,0x27,0x14,0x0a]
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amoswap.w.rl a4, ra, (s0)
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# CHECK-INST: amoadd.w.rl a1, a2, (a3)
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# CHECK: encoding: [0xaf,0xa5,0xc6,0x02]
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amoadd.w.rl a1, a2, (a3)
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# CHECK-INST: amoxor.w.rl a2, a3, (a4)
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# CHECK: encoding: [0x2f,0x26,0xd7,0x22]
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amoxor.w.rl a2, a3, (a4)
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# CHECK-INST: amoand.w.rl a3, a4, (a5)
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# CHECK: encoding: [0xaf,0xa6,0xe7,0x62]
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amoand.w.rl a3, a4, (a5)
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# CHECK-INST: amoor.w.rl a4, a5, (a6)
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# CHECK: encoding: [0x2f,0x27,0xf8,0x42]
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amoor.w.rl a4, a5, (a6)
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# CHECK-INST: amomin.w.rl a5, a6, (a7)
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# CHECK: encoding: [0xaf,0xa7,0x08,0x83]
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amomin.w.rl a5, a6, (a7)
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# CHECK-INST: amomax.w.rl s7, s6, (s5)
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# CHECK: encoding: [0xaf,0xab,0x6a,0xa3]
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||||
amomax.w.rl s7, s6, (s5)
|
||||
# CHECK-INST: amominu.w.rl s6, s5, (s4)
|
||||
# CHECK: encoding: [0x2f,0x2b,0x5a,0xc3]
|
||||
amominu.w.rl s6, s5, (s4)
|
||||
# CHECK-INST: amomaxu.w.rl s5, s4, (s3)
|
||||
# CHECK: encoding: [0xaf,0xaa,0x49,0xe3]
|
||||
amomaxu.w.rl s5, s4, (s3)
|
||||
|
||||
# CHECK-INST: amoswap.w.aqrl a4, ra, (s0)
|
||||
# CHECK: encoding: [0x2f,0x27,0x14,0x0e]
|
||||
amoswap.w.aqrl a4, ra, (s0)
|
||||
# CHECK-INST: amoadd.w.aqrl a1, a2, (a3)
|
||||
# CHECK: encoding: [0xaf,0xa5,0xc6,0x06]
|
||||
amoadd.w.aqrl a1, a2, (a3)
|
||||
# CHECK-INST: amoxor.w.aqrl a2, a3, (a4)
|
||||
# CHECK: encoding: [0x2f,0x26,0xd7,0x26]
|
||||
amoxor.w.aqrl a2, a3, (a4)
|
||||
# CHECK-INST: amoand.w.aqrl a3, a4, (a5)
|
||||
# CHECK: encoding: [0xaf,0xa6,0xe7,0x66]
|
||||
amoand.w.aqrl a3, a4, (a5)
|
||||
# CHECK-INST: amoor.w.aqrl a4, a5, (a6)
|
||||
# CHECK: encoding: [0x2f,0x27,0xf8,0x46]
|
||||
amoor.w.aqrl a4, a5, (a6)
|
||||
# CHECK-INST: amomin.w.aqrl a5, a6, (a7)
|
||||
# CHECK: encoding: [0xaf,0xa7,0x08,0x87]
|
||||
amomin.w.aqrl a5, a6, (a7)
|
||||
# CHECK-INST: amomax.w.aqrl s7, s6, (s5)
|
||||
# CHECK: encoding: [0xaf,0xab,0x6a,0xa7]
|
||||
amomax.w.aqrl s7, s6, (s5)
|
||||
# CHECK-INST: amominu.w.aqrl s6, s5, (s4)
|
||||
# CHECK: encoding: [0x2f,0x2b,0x5a,0xc7]
|
||||
amominu.w.aqrl s6, s5, (s4)
|
||||
# CHECK-INST: amomaxu.w.aqrl s5, s4, (s3)
|
||||
# CHECK: encoding: [0xaf,0xaa,0x49,0xe7]
|
||||
amomaxu.w.aqrl s5, s4, (s3)
|
||||
|
|
@ -117,6 +117,7 @@ sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemoni
|
|||
# Invalid operand types
|
||||
xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
|
||||
sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
|
||||
add a1, a2, (a3) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
|
||||
|
||||
# Too many operands
|
||||
add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
|
||||
|
|
@ -131,3 +132,4 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
|
|||
|
||||
# Instruction not in the base ISA
|
||||
mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
|
||||
amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
|
||||
|
|
|
|||
Loading…
Reference in New Issue