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AMDGPU: Improve i16/v2i16 bswap

This commit is contained in:
Matt Arsenault 2020-02-14 10:31:38 -05:00
parent 7badb38918
commit 8c2c0b3637
3 changed files with 37 additions and 28 deletions
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10
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -365,6 +365,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
// FIXME: This should be narrowed to i32, but that only happens if i64 is
// illegal.
// FIXME: Should lower sub-i32 bswaps to bit-ops without v_perm_b32.
setOperationAction(ISD::BSWAP, MVT::i64, Legal);
setOperationAction(ISD::BSWAP, MVT::i32, Legal);
@ -467,7 +468,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SREM, MVT::i16, Promote);
setOperationAction(ISD::UREM, MVT::i16, Promote);
setOperationAction(ISD::BSWAP, MVT::i16, Promote);
setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
setOperationAction(ISD::CTTZ, MVT::i16, Promote);
@ -549,6 +549,11 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
}
}
// v_perm_b32 can handle either of these.
setOperationAction(ISD::BSWAP, MVT::i16, Legal);
setOperationAction(ISD::BSWAP, MVT::v2i16, Legal);
setOperationAction(ISD::BSWAP, MVT::v4i16, Custom);
// XXX - Do these do anything? Vector constants turn into build_vector.
setOperationAction(ISD::Constant, MVT::v2i16, Legal);
setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
@ -3909,7 +3914,7 @@ SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode();
EVT VT = Op.getValueType();
assert(VT == MVT::v4f16);
assert(VT == MVT::v4f16 || VT == MVT::v4i16);
SDValue Lo, Hi;
std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
@ -4018,6 +4023,7 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FABS:
case ISD::FNEG:
case ISD::FCANONICALIZE:
case ISD::BSWAP:
return splitUnaryVectorOp(Op, DAG);
case ISD::FMINNUM:
case ISD::FMAXNUM:

18
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -1834,6 +1834,24 @@ def : GCNPat <
sub1)
>;
// Magic number: 1 | (0 << 8) | (12 << 16) | (12 << 24)
// The 12s emit 0s.
def : GCNPat <
(i16 (bswap i16:$a)),
(V_PERM_B32 (i32 0), VSrc_b32:$a, (S_MOV_B32 (i32 0x0c0c0001)))
>;
def : GCNPat <
(i32 (zext (bswap i16:$a))),
(V_PERM_B32 (i32 0), VSrc_b32:$a, (S_MOV_B32 (i32 0x0c0c0001)))
>;
// Magic number: 1 | (0 << 8) | (3 << 16) | (2 << 24)
def : GCNPat <
(v2i16 (bswap v2i16:$a)),
(V_PERM_B32 (i32 0), VSrc_b32:$a, (S_MOV_B32 (i32 0x02030001)))
>;
}
let OtherPredicates = [NoFP16Denormals] in {

37
llvm/test/CodeGen/AMDGPU/bswap.ll
View File

@ -374,9 +374,9 @@ define float @missing_truncate_promote_bswap(i32 %arg) {
; VI-LABEL: missing_truncate_promote_bswap:
; VI: ; %bb.0: ; %bb
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x10203
; VI-NEXT: s_mov_b32 s4, 0xc0c0001
; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_cvt_f32_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-NEXT: s_setpc_b64 s[30:31]
bb:
%tmp = trunc i32 %arg to i16
@ -400,9 +400,8 @@ define i16 @v_bswap_i16(i16 %src) {
; VI-LABEL: v_bswap_i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x10203
; VI-NEXT: s_mov_b32 s4, 0xc0c0001
; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
ret i16 %bswap
@ -422,9 +421,8 @@ define i32 @v_bswap_i16_zext_to_i32(i16 %src) {
; VI-LABEL: v_bswap_i16_zext_to_i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x10203
; VI-NEXT: s_mov_b32 s4, 0xc0c0001
; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = zext i16 %bswap to i32
@ -445,9 +443,9 @@ define i32 @v_bswap_i16_sext_to_i32(i16 %src) {
; VI-LABEL: v_bswap_i16_sext_to_i32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x10203
; VI-NEXT: s_mov_b32 s4, 0xc0c0001
; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
; VI-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = sext i16 %bswap to i32
@ -474,11 +472,8 @@ define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {
; VI-LABEL: v_bswap_v2i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-NEXT: s_mov_b32 s4, 0x10203
; VI-NEXT: v_perm_b32 v1, 0, v1, s4
; VI-NEXT: s_mov_b32 s4, 0x2030001
; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src)
ret <2 x i16> %bswap
@ -508,13 +503,9 @@ define <3 x i16> @v_bswap_v3i16(<3 x i16> %src) {
; VI-LABEL: v_bswap_v3i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x10203
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; VI-NEXT: v_perm_b32 v1, 0, v1, s4
; VI-NEXT: v_perm_b32 v2, 0, v2, s4
; VI-NEXT: s_mov_b32 s4, 0x2030001
; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_perm_b32 v1, 0, v1, s4
; VI-NEXT: s_setpc_b64 s[30:31]
%bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %src)
ret <3 x i16> %bswap
@ -551,15 +542,9 @@ define <4 x i16> @v_bswap_v4i16(<4 x i16> %src) {
; VI-LABEL: v_bswap_v4i16:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; VI-NEXT: s_mov_b32 s4, 0x10203
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_perm_b32 v2, 0, v2, s4
; VI-NEXT: v_perm_b32 v1, 0, v1, s4
; VI-NEXT: v_perm_b32 v3, 0, v3, s4
; VI-NEXT: s_mov_b32 s4, 0x2030001
; VI-NEXT: v_perm_b32 v0, 0, v0, s4
; VI-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_perm_b32 v1, 0, v1, s4
; VI-NEXT: s_setpc_b64 s[30:31]
%bswap = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %src)
ret <4 x i16> %bswap