forked from OSchip/llvm-project
parent
6fbb7bbcc6
commit
8c1f17bb98
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@ -256,8 +256,7 @@ Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Use, bool FirstInSelfLoop) {
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return HighLatencyCPSR || FirstInSelfLoop;
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SmallSet<unsigned, 2> Defs;
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for (unsigned i = 0, e = CPSRDef->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = CPSRDef->getOperand(i);
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for (const MachineOperand &MO : CPSRDef->operands()) {
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if (!MO.isReg() || MO.isUndef() || MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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@ -266,8 +265,7 @@ Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Use, bool FirstInSelfLoop) {
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Defs.insert(Reg);
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}
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for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = Use->getOperand(i);
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for (const MachineOperand &MO : Use->operands()) {
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if (!MO.isReg() || MO.isUndef() || MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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@ -858,8 +856,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
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static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
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bool HasDef = false;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || MO.isUndef() || MO.isUse())
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continue;
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if (MO.getReg() != ARM::CPSR)
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@ -874,8 +871,7 @@ static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
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}
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static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg() || MO.isUndef() || MO.isDef())
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continue;
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if (MO.getReg() != ARM::CPSR)
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