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[X86][SSE] Ensure that vector shift-by-immediate inputs are correctly bitcast to the result type 

vXi8/vXi64 vector shifts are often shifted as vYi16/vYi32 types but we weren't always remembering to bitcast the input.

Tested with a new assert as we don't currently manipulate these shifts enough for test cases to catch them.

llvm-svn: 294308
This commit is contained in:
Simon Pilgrim 2017-02-07 14:22:25 +00:00
parent b3d0b2d018
commit 8c0f62d293
1 changed files with 10 additions and 6 deletions
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16
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -18479,6 +18479,11 @@ static SDValue getTargetVShiftByConstNode(unsigned Opc, const SDLoc &dl, MVT VT,
SelectionDAG &DAG) {
MVT ElementType = VT.getVectorElementType();
// Bitcast the source vector to the output type, this is mainly necessary for
// vXi8/vXi64 shifts.
if (VT != SrcOp.getSimpleValueType())
SrcOp = DAG.getBitcast(VT, SrcOp);
// Fold this packed shift into its first operand if ShiftAmt is 0.
if (ShiftAmt == 0)
return SrcOp;
@ -18495,9 +18500,8 @@ static SDValue getTargetVShiftByConstNode(unsigned Opc, const SDLoc &dl, MVT VT,
&& "Unknown target vector shift-by-constant node");
// Fold this packed vector shift into a build vector if SrcOp is a
// vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
if (VT == SrcOp.getSimpleValueType() &&
ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
// vector of Constants or UNDEFs.
if (ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
SmallVector<SDValue, 8> Elts;
unsigned NumElts = SrcOp->getNumOperands();
ConstantSDNode *ND;
@ -30523,8 +30527,10 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
"Unexpected shift opcode");
bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode;
EVT VT = N->getValueType(0);
SDValue N0 = N->getOperand(0);
unsigned NumBitsPerElt = VT.getScalarSizeInBits();
assert((NumBitsPerElt % 8) == 0);
assert(VT == N0.getValueType() && (NumBitsPerElt % 8) == 0 &&
"Unexpected value type");
// Out of range logical bit shifts are guaranteed to be zero.
// Out of range arithmetic bit shifts splat the sign bit.
@ -30536,8 +30542,6 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
ShiftVal = NumBitsPerElt - 1;
}
SDValue N0 = N->getOperand(0);
// Shift N0 by zero -> N0.
if (!ShiftVal)
return N0;