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[ARM] FP16 mov imm pattern 

This is a follow up of r324321, adding a match pattern for mov with a FP16
immediate (also fixing operand vfp_f16imm that wasn't even compiling).

Differential Revision: https://reviews.llvm.org/D42973

llvm-svn: 324456
This commit is contained in:
Sjoerd Meijer 2018-02-07 08:37:17 +00:00
parent 5f133dc99b
commit 8c0739347c
2 changed files with 17 additions and 3 deletions
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7
llvm/lib/Target/ARM/ARMInstrVFP.td
View File

@ -44,7 +44,7 @@ def vfp_f16imm : Operand<f16>,
}], SDNodeXForm<fpimm, [{
APFloat InVal = N->getValueAPF();
uint32_t enc = ARM_AM::getFP16Imm(InVal);
return CurDAG->getTargetConstant(enc, MVT::i32);
return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
}]>> {
let PrintMethod = "printFPImmOperand";
let ParserMatchClass = FPImmOperand;
@ -2343,10 +2343,11 @@ def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
let Inst{3-0} = imm{3-0};
}
def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),
def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm),
VFPMiscFrm, IIC_fpUNA16,
"vmov", ".f16\t$Sd, $imm",
[]>, Requires<[HasFullFP16]> {
[(set HPR:$Sd, vfp_f16imm:$imm)]>,
Requires<[HasFullFP16]> {
bits<5> Sd;
bits<8> imm;

13
llvm/test/CodeGen/ARM/fp16-instructions.ll
View File

@ -471,7 +471,20 @@ entry:
; TODO: fix immediates.
; 21. VMOV (between general-purpose register and half-precision register)
; 22. VMOV (immediate)
define i32 @movi(i32 %a.coerce) {
entry:
%tmp.0.extract.trunc = trunc i32 %a.coerce to i16
%0 = bitcast i16 %tmp.0.extract.trunc to half
%add = fadd half %0, 0xHC000
%1 = bitcast half %add to i16
%tmp2.0.insert.ext = zext i16 %1 to i32
ret i32 %tmp2.0.insert.ext
; CHECK-LABEL: movi:
; CHECK-HARDFP-FULLFP16: vmov.f16 s0, #-2.000000e+00
}
; 23. VMUL
define float @Mul(float %a.coerce, float %b.coerce) {