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[DAGCombiner] allow undef elts in vector fmul matching 

llvm-svn: 344534
This commit is contained in:
Sanjay Patel 2018-10-15 16:54:07 +00:00
parent bc8aee15a2
commit 8bd74785f0
2 changed files with 5 additions and 7 deletions
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2
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -10898,7 +10898,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
auto isFMulNegTwo = [](SDValue FMul) {
if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL)
return false;
auto *C = isConstOrConstSplatFP(FMul.getOperand(1));
auto *C = isConstOrConstSplatFP(FMul.getOperand(1), true);
return C && C->isExactlyValue(-2.0);
};

10
llvm/test/CodeGen/AArch64/fadd-combines.ll
View File

@ -76,9 +76,8 @@ define <4 x float> @fmulnegtwo_vec_commute(<4 x float> %a, <4 x float> %b) {
define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: fmulnegtwo_vec_undefs:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #192, lsl #24
; CHECK-NEXT: fmul v1.4s, v1.4s, v2.4s
; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: fadd v1.4s, v1.4s, v1.4s
; CHECK-NEXT: fsub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%mul = fmul <4 x float> %b, <float undef, float -2.0, float undef, float -2.0>
%add = fadd <4 x float> %a, %mul
@ -88,9 +87,8 @@ define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) {
define <4 x float> @fmulnegtwo_vec_commute_undefs(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: fmulnegtwo_vec_commute_undefs:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.4s, #192, lsl #24
; CHECK-NEXT: fmul v1.4s, v1.4s, v2.4s
; CHECK-NEXT: fadd v0.4s, v1.4s, v0.4s
; CHECK-NEXT: fadd v1.4s, v1.4s, v1.4s
; CHECK-NEXT: fsub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret
%mul = fmul <4 x float> %b, <float -2.0, float undef, float -2.0, float -2.0>
%add = fadd <4 x float> %mul, %a