From 8bd74785f0a29510805fa38a3e4f4bd8b6bceefd Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 15 Oct 2018 16:54:07 +0000 Subject: [PATCH] [DAGCombiner] allow undef elts in vector fmul matching llvm-svn: 344534 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- llvm/test/CodeGen/AArch64/fadd-combines.ll | 10 ++++------ 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index ab871a25d073..11cc699ffe1e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -10898,7 +10898,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { auto isFMulNegTwo = [](SDValue FMul) { if (!FMul.hasOneUse() || FMul.getOpcode() != ISD::FMUL) return false; - auto *C = isConstOrConstSplatFP(FMul.getOperand(1)); + auto *C = isConstOrConstSplatFP(FMul.getOperand(1), true); return C && C->isExactlyValue(-2.0); }; diff --git a/llvm/test/CodeGen/AArch64/fadd-combines.ll b/llvm/test/CodeGen/AArch64/fadd-combines.ll index c2e4430029ad..7332101a481e 100644 --- a/llvm/test/CodeGen/AArch64/fadd-combines.ll +++ b/llvm/test/CodeGen/AArch64/fadd-combines.ll @@ -76,9 +76,8 @@ define <4 x float> @fmulnegtwo_vec_commute(<4 x float> %a, <4 x float> %b) { define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: fmulnegtwo_vec_undefs: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v2.4s, #192, lsl #24 -; CHECK-NEXT: fmul v1.4s, v1.4s, v2.4s -; CHECK-NEXT: fadd v0.4s, v0.4s, v1.4s +; CHECK-NEXT: fadd v1.4s, v1.4s, v1.4s +; CHECK-NEXT: fsub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %mul = fmul <4 x float> %b, %add = fadd <4 x float> %a, %mul @@ -88,9 +87,8 @@ define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) { define <4 x float> @fmulnegtwo_vec_commute_undefs(<4 x float> %a, <4 x float> %b) { ; CHECK-LABEL: fmulnegtwo_vec_commute_undefs: ; CHECK: // %bb.0: -; CHECK-NEXT: movi v2.4s, #192, lsl #24 -; CHECK-NEXT: fmul v1.4s, v1.4s, v2.4s -; CHECK-NEXT: fadd v0.4s, v1.4s, v0.4s +; CHECK-NEXT: fadd v1.4s, v1.4s, v1.4s +; CHECK-NEXT: fsub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: ret %mul = fmul <4 x float> %b, %add = fadd <4 x float> %mul, %a