forked from OSchip/llvm-project
[MCA] Fix CarryOver check in the DispatchStage (PR50174).
Early exit from method DispatchStage::isAvailable() if the dispatch group is already full. Not all instructions declare at least one uOP. Fixes PR50174.
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@ -156,6 +156,10 @@ Error DispatchStage::cycleStart() {
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}
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bool DispatchStage::isAvailable(const InstRef &IR) const {
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// Conservatively bail out if there are no available dispatch entries.
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if (!AvailableEntries)
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return false;
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const Instruction &Inst = *IR.getInstruction();
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unsigned NumMicroOps = Inst.getNumMicroOps();
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const InstrDesc &Desc = Inst.getDesc();
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@ -0,0 +1,85 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=thumbv7-gnueabihf-linux -mcpu=cortex-a57 -timeline -iterations=10 < %s | FileCheck %s
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# Test case from PR50174.
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# NOP consumes zero resources, and it is 0 uOPs.
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pop {r3, r4, r5, r6, r7, pc}
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nop
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# CHECK: Iterations: 10
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# CHECK-NEXT: Instructions: 20
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# CHECK-NEXT: Total Cycles: 43
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# CHECK-NEXT: Total uOps: 80
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# CHECK: Dispatch Width: 3
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# CHECK-NEXT: uOps Per Cycle: 1.86
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# CHECK-NEXT: IPC: 0.47
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# CHECK-NEXT: Block RThroughput: 4.0
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 8 4 4.00 * U pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: 0 0 0.00 * * U nop
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# CHECK: Resources:
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# CHECK-NEXT: [0] - A57UnitB
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# CHECK-NEXT: [1.0] - A57UnitI
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# CHECK-NEXT: [1.1] - A57UnitI
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# CHECK-NEXT: [2] - A57UnitL
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# CHECK-NEXT: [3] - A57UnitM
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# CHECK-NEXT: [4] - A57UnitS
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# CHECK-NEXT: [5] - A57UnitW
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# CHECK-NEXT: [6] - A57UnitX
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6]
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# CHECK-NEXT: - 2.00 2.00 4.00 - - - -
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0] [1.0] [1.1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: - 2.00 2.00 4.00 - - - - pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: - - - - - - - - nop
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# CHECK: Timeline view:
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# CHECK-NEXT: 0123456789 0123456789
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# CHECK-NEXT: Index 0123456789 0123456789 012
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# CHECK: [0,0] DeeeeER . . . . . . . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [0,1] . D---R . . . . . . . . nop
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# CHECK-NEXT: [1,0] . D=eeeeER . . . . . . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [1,1] . D----R . . . . . . . nop
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# CHECK-NEXT: [2,0] . .D==eeeeER. . . . . . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [2,1] . . DE----R. . . . . . . nop
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# CHECK-NEXT: [3,0] . . D===eeeeER . . . . . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [3,1] . . .D=E----R . . . . . . nop
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# CHECK-NEXT: [4,0] . . . D====eeeeER . . . . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [4,1] . . . D==E----R . . . . . nop
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# CHECK-NEXT: [5,0] . . . D=====eeeeER . . . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [5,1] . . . . D===E----R . . . . nop
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# CHECK-NEXT: [6,0] . . . . D======eeeeER . . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [6,1] . . . . D====E----R . . . nop
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# CHECK-NEXT: [7,0] . . . . .D=======eeeeER. . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [7,1] . . . . . D=====E----R. . . nop
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# CHECK-NEXT: [8,0] . . . . . D========eeeeER . . pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [8,1] . . . . . .D======E----R . . nop
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# CHECK-NEXT: [9,0] . . . . . . D=========eeeeER pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: [9,1] . . . . . . D=======E----R nop
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 10 5.5 0.1 0.0 pop {r3, r4, r5, r6, r7, pc}
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# CHECK-NEXT: 1. 10 3.6 0.0 3.9 nop
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# CHECK-NEXT: 10 4.6 0.1 2.0 <total>
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