forked from OSchip/llvm-project
[clang][AArch64][SVE] Implement conditional operator for SVE vectors
This patch adds support for the conditional (ternary) operator on SVE scalable vector types in C++, matching the behaviour for NEON vector types. Like the conditional operator for NEON types, this is disabled in C mode. Differential Revision: https://reviews.llvm.org/D124091
This commit is contained in:
David Truby
parent
8b42e6d057
commit
8bc29d1427
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@ -11974,6 +11974,10 @@ public:
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QualType CheckVectorConditionalTypes(ExprResult &Cond, ExprResult &LHS,
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ExprResult &RHS,
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SourceLocation QuestionLoc);
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QualType CheckSizelessVectorConditionalTypes(ExprResult &Cond,
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ExprResult &LHS, ExprResult &RHS,
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SourceLocation QuestionLoc);
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QualType FindCompositePointerType(SourceLocation Loc, Expr *&E1, Expr *&E2,
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bool ConvertArgs = true);
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QualType FindCompositePointerType(SourceLocation Loc,
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@ -4642,7 +4642,8 @@ VisitAbstractConditionalOperator(const AbstractConditionalOperator *E) {
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return tmp5;
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}
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if (condExpr->getType()->isVectorType()) {
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if (condExpr->getType()->isVectorType() ||
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condExpr->getType()->isVLSTBuiltinType()) {
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CGF.incrementProfileCounter(E);
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llvm::Value *CondV = CGF.EmitScalarExpr(condExpr);
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@ -23,6 +23,7 @@
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#include "clang/AST/RecursiveASTVisitor.h"
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#include "clang/AST/TypeLoc.h"
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#include "clang/Basic/AlignedAllocation.h"
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#include "clang/Basic/DiagnosticSema.h"
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#include "clang/Basic/PartialDiagnostic.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TypeTraits.h"
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@ -40,6 +41,7 @@
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TypeSize.h"
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using namespace clang;
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using namespace sema;
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@ -6108,6 +6110,16 @@ static bool isValidVectorForConditionalCondition(ASTContext &Ctx,
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return EltTy->isIntegralType(Ctx);
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}
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static bool isValidSizelessVectorForConditionalCondition(ASTContext &Ctx,
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QualType CondTy) {
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if (!CondTy->isVLSTBuiltinType())
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return false;
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const QualType EltTy =
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cast<BuiltinType>(CondTy.getCanonicalType())->getSveEltType(Ctx);
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assert(!EltTy->isEnumeralType() && "Vectors cant be enum types");
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return EltTy->isIntegralType(Ctx);
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}
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QualType Sema::CheckVectorConditionalTypes(ExprResult &Cond, ExprResult &LHS,
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ExprResult &RHS,
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SourceLocation QuestionLoc) {
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@ -6199,6 +6211,89 @@ QualType Sema::CheckVectorConditionalTypes(ExprResult &Cond, ExprResult &LHS,
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return ResultType;
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}
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QualType Sema::CheckSizelessVectorConditionalTypes(ExprResult &Cond,
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ExprResult &LHS,
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ExprResult &RHS,
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SourceLocation QuestionLoc) {
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LHS = DefaultFunctionArrayLvalueConversion(LHS.get());
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RHS = DefaultFunctionArrayLvalueConversion(RHS.get());
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QualType CondType = Cond.get()->getType();
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const auto *CondBT = CondType->castAs<BuiltinType>();
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QualType CondElementTy = CondBT->getSveEltType(Context);
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llvm::ElementCount CondElementCount =
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Context.getBuiltinVectorTypeInfo(CondBT).EC;
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QualType LHSType = LHS.get()->getType();
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const auto *LHSBT =
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LHSType->isVLSTBuiltinType() ? LHSType->getAs<BuiltinType>() : nullptr;
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QualType RHSType = RHS.get()->getType();
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const auto *RHSBT =
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RHSType->isVLSTBuiltinType() ? RHSType->getAs<BuiltinType>() : nullptr;
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QualType ResultType;
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if (LHSBT && RHSBT) {
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// If both are sizeless vector types, they must be the same type.
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if (!Context.hasSameType(LHSType, RHSType)) {
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Diag(QuestionLoc, diag::err_conditional_vector_mismatched)
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<< LHSType << RHSType;
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return QualType();
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}
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ResultType = LHSType;
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} else if (LHSBT || RHSBT) {
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ResultType = CheckSizelessVectorOperands(
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LHS, RHS, QuestionLoc, /*IsCompAssign*/ false, ACK_Conditional);
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if (ResultType.isNull())
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return QualType();
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} else {
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// Both are scalar so splat
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QualType ResultElementTy;
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LHSType = LHSType.getCanonicalType().getUnqualifiedType();
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RHSType = RHSType.getCanonicalType().getUnqualifiedType();
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if (Context.hasSameType(LHSType, RHSType))
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ResultElementTy = LHSType;
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else
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ResultElementTy =
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UsualArithmeticConversions(LHS, RHS, QuestionLoc, ACK_Conditional);
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if (ResultElementTy->isEnumeralType()) {
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Diag(QuestionLoc, diag::err_conditional_vector_operand_type)
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<< ResultElementTy;
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return QualType();
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}
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ResultType = Context.getScalableVectorType(
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ResultElementTy, CondElementCount.getKnownMinValue());
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LHS = ImpCastExprToType(LHS.get(), ResultType, CK_VectorSplat);
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RHS = ImpCastExprToType(RHS.get(), ResultType, CK_VectorSplat);
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}
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assert(!ResultType.isNull() && ResultType->isVLSTBuiltinType() &&
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"Result should have been a vector type");
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auto *ResultBuiltinTy = ResultType->castAs<BuiltinType>();
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QualType ResultElementTy = ResultBuiltinTy->getSveEltType(Context);
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llvm::ElementCount ResultElementCount =
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Context.getBuiltinVectorTypeInfo(ResultBuiltinTy).EC;
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if (ResultElementCount != CondElementCount) {
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Diag(QuestionLoc, diag::err_conditional_vector_size)
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<< CondType << ResultType;
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return QualType();
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}
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if (Context.getTypeSize(ResultElementTy) !=
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Context.getTypeSize(CondElementTy)) {
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Diag(QuestionLoc, diag::err_conditional_vector_element_size)
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<< CondType << ResultType;
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return QualType();
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}
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return ResultType;
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}
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/// Check the operands of ?: under C++ semantics.
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///
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/// See C++ [expr.cond]. Note that LHS is never null, even for the GNU x ?: y
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@ -6232,10 +6327,14 @@ QualType Sema::CXXCheckConditionalOperands(ExprResult &Cond, ExprResult &LHS,
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bool IsVectorConditional =
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isValidVectorForConditionalCondition(Context, Cond.get()->getType());
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bool IsSizelessVectorConditional =
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isValidSizelessVectorForConditionalCondition(Context,
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Cond.get()->getType());
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// C++11 [expr.cond]p1
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// The first expression is contextually converted to bool.
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if (!Cond.get()->isTypeDependent()) {
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ExprResult CondRes = IsVectorConditional
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ExprResult CondRes = IsVectorConditional || IsSizelessVectorConditional
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? DefaultFunctionArrayLvalueConversion(Cond.get())
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: CheckCXXBooleanCondition(Cond.get());
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if (CondRes.isInvalid())
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@ -6304,6 +6403,9 @@ QualType Sema::CXXCheckConditionalOperands(ExprResult &Cond, ExprResult &LHS,
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if (IsVectorConditional)
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return CheckVectorConditionalTypes(Cond, LHS, RHS, QuestionLoc);
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if (IsSizelessVectorConditional)
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return CheckSizelessVectorConditionalTypes(Cond, LHS, RHS, QuestionLoc);
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// C++11 [expr.cond]p3
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// Otherwise, if the second and third operand have different types, and
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// either has (cv) class type [...] an attempt is made to convert each of
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@ -0,0 +1,224 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
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// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone \
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// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s
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// REQUIRES: aarch64-registered-target
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#include <arm_sve.h>
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// CHECK-LABEL: @_Z9cond_boolu10__SVBool_tu10__SVBool_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i1> [[CMP]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i1> [[A]], <vscale x 16 x i1> [[B]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[VECTOR_SELECT]]
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//
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svbool_t cond_bool(svbool_t a, svbool_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z7cond_i8u10__SVInt8_tu10__SVInt8_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i8> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i8> [[A]], <vscale x 16 x i8> [[B]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[VECTOR_SELECT]]
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//
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svint8_t cond_i8(svint8_t a, svint8_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z7cond_u8u11__SVUint8_tu11__SVUint8_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i8> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i8> [[A]], <vscale x 16 x i8> [[B]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[VECTOR_SELECT]]
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//
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svuint8_t cond_u8(svuint8_t a, svuint8_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_i16u11__SVInt16_tu11__SVInt16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x i16> [[A]], <vscale x 8 x i16> [[B]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[VECTOR_SELECT]]
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//
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svint16_t cond_i16(svint16_t a, svint16_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_u16u12__SVUint16_tu12__SVUint16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x i16> [[A]], <vscale x 8 x i16> [[B]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[VECTOR_SELECT]]
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//
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svuint16_t cond_u16(svuint16_t a, svuint16_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_i32u11__SVInt32_tu11__SVInt32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
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//
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svint32_t cond_i32(svint32_t a, svint32_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_u32u12__SVUint32_tu12__SVUint32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
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//
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svuint32_t cond_u32(svuint32_t a, svuint32_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_i64u11__SVInt64_tu11__SVInt64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> [[B]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
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//
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svint64_t cond_i64(svint64_t a, svint64_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_u64u12__SVUint64_tu12__SVUint64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> [[B]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
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//
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svuint64_t cond_u64(svuint64_t a, svuint64_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_f16u13__SVFloat16_tu13__SVFloat16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x half> [[A]], <vscale x 8 x half> [[B]]
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// CHECK-NEXT: ret <vscale x 8 x half> [[VECTOR_SELECT]]
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//
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svfloat16_t cond_f16(svfloat16_t a, svfloat16_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_f32u13__SVFloat32_tu13__SVFloat32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]]
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// CHECK-NEXT: ret <vscale x 4 x float> [[VECTOR_SELECT]]
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//
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svfloat32_t cond_f32(svfloat32_t a, svfloat32_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_f64u13__SVFloat64_tu13__SVFloat64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x double> [[A]], <vscale x 2 x double> [[B]]
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// CHECK-NEXT: ret <vscale x 2 x double> [[VECTOR_SELECT]]
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//
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svfloat64_t cond_f64(svfloat64_t a, svfloat64_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z14cond_i32_splatu11__SVInt32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], zeroinitializer
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> zeroinitializer
|
||||
// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
|
||||
//
|
||||
svint32_t cond_i32_splat(svint32_t a) {
|
||||
return a < 0 ? a : 0;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @_Z14cond_u32_splatu12__SVUint32_t(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
|
||||
// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
|
||||
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
|
||||
// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
|
||||
//
|
||||
svuint32_t cond_u32_splat(svuint32_t a) {
|
||||
return a < 1u ? a : 1u;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @_Z14cond_i64_splatu11__SVInt64_t(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], zeroinitializer
|
||||
// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
|
||||
// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
|
||||
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> zeroinitializer
|
||||
// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
|
||||
//
|
||||
svint64_t cond_i64_splat(svint64_t a) {
|
||||
return a < 0l ? a : 0l;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @_Z14cond_u64_splatu12__SVUint64_t(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
|
||||
// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
|
||||
// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
|
||||
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
|
||||
// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
|
||||
//
|
||||
svuint64_t cond_u64_splat(svuint64_t a) {
|
||||
return a < 1ul ? a : 1ul;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @_Z14cond_f32_splatu13__SVFloat32_t(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], zeroinitializer
|
||||
// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
|
||||
// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
|
||||
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x float> [[A]], <vscale x 4 x float> zeroinitializer
|
||||
// CHECK-NEXT: ret <vscale x 4 x float> [[VECTOR_SELECT]]
|
||||
//
|
||||
svfloat32_t cond_f32_splat(svfloat32_t a) {
|
||||
return a < 0.f ? a : 0.f;
|
||||
}
|
||||
|
||||
// CHECK-LABEL: @_Z14cond_f64_splatu13__SVFloat64_t(
|
||||
// CHECK-NEXT: entry:
|
||||
// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 2 x double> [[A:%.*]], zeroinitializer
|
||||
// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
|
||||
// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
|
||||
// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x double> [[A]], <vscale x 2 x double> zeroinitializer
|
||||
// CHECK-NEXT: ret <vscale x 2 x double> [[VECTOR_SELECT]]
|
||||
//
|
||||
svfloat64_t cond_f64_splat(svfloat64_t a) {
|
||||
return a < 0. ? a : 0.;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
// RUN: %clang_cc1 -verify -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only %s
|
||||
|
||||
// REQUIRES: aarch64-registered-target
|
||||
|
||||
#include <arm_sve.h>
|
||||
|
||||
void cond(svint8_t i8, svint16_t i16, svint32_t i32, svint64_t i64,
|
||||
svuint8_t u8, svuint16_t u16, svuint32_t u32, svuint64_t u64,
|
||||
svfloat16_t f16, svfloat32_t f32, svfloat64_t f64,
|
||||
svbool_t b) {
|
||||
(void) i8 < i8 ? i16 : i16; // expected-error{{invalid operands to binary expression}}
|
||||
(void) i8 < i8 ? i32 : i32; // expected-error{{invalid operands to binary expression}}
|
||||
(void) i8 < i8 ? i64 : i64; // expected-error{{invalid operands to binary expression}}
|
||||
|
||||
(void) i16 < i16 ? i16 : i8; // expected-error{{invalid operands to binary expression}}
|
||||
(void) i16 < i16 ? i16 : i32; // expected-error{{invalid operands to binary expression}}
|
||||
(void) i16 < i16 ? i16 : i64; // expected-error{{invalid operands to binary expression}}
|
||||
|
||||
(void) i16 < i16 ? i8 : i16; // expected-error{{invalid operands to binary expression}}
|
||||
(void) i16 < i16 ? i32 : i16; // expected-error{{invalid operands to binary expression}}
|
||||
(void) i16 < i16 ? i64 : i16; // expected-error{{invalid operands to binary expression}}
|
||||
}
|
||||
Loading…
Reference in New Issue