forked from OSchip/llvm-project
[AVX-512] Add NoVLX Predicates to some patterns so they don't rely on pattern ordering to be lower priority than their equivalent VLX pattern.
llvm-svn: 280462
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c5d41d4ada
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llvm/lib/Target/X86
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@ -1654,6 +1654,7 @@ defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
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avx512vl_i64_info, HasAVX512>,
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avx512vl_i64_info, HasAVX512>,
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T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
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T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
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let Predicates = [HasAVX512, NoVLX] in {
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def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
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def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
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(COPY_TO_REGCLASS (VPCMPGTDZrr
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(COPY_TO_REGCLASS (VPCMPGTDZrr
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
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@ -1663,6 +1664,7 @@ def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
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(COPY_TO_REGCLASS (VPCMPEQDZrr
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(COPY_TO_REGCLASS (VPCMPEQDZrr
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
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(v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
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}
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multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
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multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
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X86VectorVTInfo _> {
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X86VectorVTInfo _> {
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