forked from OSchip/llvm-project
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
llvm-svn: 77939
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@ -421,8 +421,12 @@ int llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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if (AddrMode == ARMII::AddrMode5)
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// FIXME: Not consistent.
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ImmedOffset |= 1 << NumBits;
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else
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else {
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ImmedOffset = -ImmedOffset;
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if (ImmedOffset == 0)
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// Change the opcode back if the encoded offset is zero.
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MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
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}
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}
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ImmOp.ChangeToImmediate(ImmedOffset);
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Offset &= ~(Mask*Scale);
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@ -0,0 +1,85 @@
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; RUN: llvm-as < %s | llc -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s
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@csize = external global [100 x [20 x [4 x i8]]] ; <[100 x [20 x [4 x i8]]]*> [#uses=1]
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@vsize = external global [100 x [20 x [4 x i8]]] ; <[100 x [20 x [4 x i8]]]*> [#uses=1]
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@cll = external global [20 x [10 x i8]] ; <[20 x [10 x i8]]*> [#uses=1]
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@lefline = external global [100 x [20 x i32]] ; <[100 x [20 x i32]]*> [#uses=1]
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@sep = external global [20 x i32] ; <[20 x i32]*> [#uses=1]
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define arm_apcscc void @main(i32 %argc, i8** %argv) noreturn nounwind {
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; CHECK: main:
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; CHECK: ldrb.w
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entry:
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%nb.i.i.i = alloca [25 x i8], align 1 ; <[25 x i8]*> [#uses=0]
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%line.i.i.i = alloca [200 x i8], align 1 ; <[200 x i8]*> [#uses=1]
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%line.i = alloca [1024 x i8], align 1 ; <[1024 x i8]*> [#uses=0]
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br i1 undef, label %bb.i.i, label %bb4.preheader.i
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bb.i.i: ; preds = %entry
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unreachable
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bb4.preheader.i: ; preds = %entry
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br i1 undef, label %tbl.exit, label %bb.i.preheader
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bb.i.preheader: ; preds = %bb4.preheader.i
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%line3.i.i.i = getelementptr [200 x i8]* %line.i.i.i, i32 0, i32 0 ; <i8*> [#uses=1]
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br label %bb.i
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bb.i: ; preds = %bb4.backedge.i, %bb.i.preheader
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br i1 undef, label %bb3.i, label %bb4.backedge.i
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bb3.i: ; preds = %bb.i
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br i1 undef, label %bb2.i184.i.i, label %bb.i183.i.i
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bb.i183.i.i: ; preds = %bb.i183.i.i, %bb3.i
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br i1 undef, label %bb2.i184.i.i, label %bb.i183.i.i
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bb2.i184.i.i: ; preds = %bb.i183.i.i, %bb3.i
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br i1 undef, label %bb5.i185.i.i, label %bb35.preheader.i.i.i
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bb35.preheader.i.i.i: ; preds = %bb2.i184.i.i
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%0 = load i8* %line3.i.i.i, align 1 ; <i8> [#uses=1]
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%1 = icmp eq i8 %0, 59 ; <i1> [#uses=1]
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br i1 %1, label %bb36.i.i.i, label %bb9.i186.i.i
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bb5.i185.i.i: ; preds = %bb2.i184.i.i
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br label %bb.i171.i.i
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bb9.i186.i.i: ; preds = %bb35.preheader.i.i.i
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unreachable
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bb36.i.i.i: ; preds = %bb35.preheader.i.i.i
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br label %bb.i171.i.i
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bb.i171.i.i: ; preds = %bb3.i176.i.i, %bb36.i.i.i, %bb5.i185.i.i
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%2 = phi i32 [ %4, %bb3.i176.i.i ], [ 0, %bb36.i.i.i ], [ 0, %bb5.i185.i.i ] ; <i32> [#uses=6]
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%scevgep16.i.i.i = getelementptr [20 x i32]* @sep, i32 0, i32 %2 ; <i32*> [#uses=1]
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%scevgep18.i.i.i = getelementptr [20 x [10 x i8]]* @cll, i32 0, i32 %2, i32 0 ; <i8*> [#uses=0]
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store i32 -1, i32* %scevgep16.i.i.i, align 4
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br label %bb1.i175.i.i
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bb1.i175.i.i: ; preds = %bb1.i175.i.i, %bb.i171.i.i
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%i.03.i172.i.i = phi i32 [ 0, %bb.i171.i.i ], [ %3, %bb1.i175.i.i ] ; <i32> [#uses=4]
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%scevgep11.i.i.i = getelementptr [100 x [20 x i32]]* @lefline, i32 0, i32 %i.03.i172.i.i, i32 %2 ; <i32*> [#uses=1]
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%scevgep12.i.i.i = getelementptr [100 x [20 x [4 x i8]]]* @vsize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0 ; <i8*> [#uses=1]
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%scevgep13.i.i.i = getelementptr [100 x [20 x [4 x i8]]]* @csize, i32 0, i32 %i.03.i172.i.i, i32 %2, i32 0 ; <i8*> [#uses=0]
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store i8 0, i8* %scevgep12.i.i.i, align 1
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store i32 0, i32* %scevgep11.i.i.i, align 4
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store i32 108, i32* undef, align 4
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%3 = add i32 %i.03.i172.i.i, 1 ; <i32> [#uses=2]
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%exitcond.i174.i.i = icmp eq i32 %3, 100 ; <i1> [#uses=1]
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br i1 %exitcond.i174.i.i, label %bb3.i176.i.i, label %bb1.i175.i.i
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bb3.i176.i.i: ; preds = %bb1.i175.i.i
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%4 = add i32 %2, 1 ; <i32> [#uses=1]
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br i1 undef, label %bb5.i177.i.i, label %bb.i171.i.i
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bb5.i177.i.i: ; preds = %bb3.i176.i.i
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unreachable
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bb4.backedge.i: ; preds = %bb.i
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br i1 undef, label %tbl.exit, label %bb.i
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tbl.exit: ; preds = %bb4.backedge.i, %bb4.preheader.i
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unreachable
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}
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