forked from OSchip/llvm-project
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move the constant pool to .text correctly print loads of labels mark R0, R1, R2 and R3 as caller save llvm-svn: 29451
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@ -43,8 +43,8 @@ namespace {
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Data32bitsDirective = "\t.word\t";
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Data64bitsDirective = 0;
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ZeroDirective = "\t.skip\t";
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CommentString = "!";
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ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
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CommentString = "#";
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ConstantPoolSection = "\t.text\n";
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AlignmentIsInBytes = false;
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}
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@ -60,9 +60,21 @@ namespace {
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}
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void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
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printOperand(MI, OpNo + 1);
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O << ", ";
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printOperand(MI, OpNo);
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const MachineOperand &MO1 = MI->getOperand(OpNo);
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const MachineOperand &MO2 = MI->getOperand(OpNo + 1);
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assert(MO1.isImmediate());
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if (MO2.isConstantPoolIndex()) {
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printOperand(MI, OpNo + 1);
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} else if (MO2.isRegister()) {
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O << '[';
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printOperand(MI, OpNo + 1);
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O << ", ";
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printOperand(MI, OpNo);
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O << ']';
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} else {
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assert(0 && "Invalid Operand Type");
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}
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}
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void printOperand(const MachineInstr *MI, int opNum);
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@ -57,10 +57,12 @@ let isReturn = 1 in {
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def bx: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
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}
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def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
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let Defs = [R0, R1, R2, R3] in {
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def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
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}
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def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
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"ldr $dst, [$addr]",
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"ldr $dst, $addr",
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[(set IntRegs:$dst, (load iaddr:$addr))]>;
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def str : InstARM<(ops IntRegs:$src, IntRegs:$addr),
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