forked from OSchip/llvm-project
[mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
asm ("ldi.w %w0, 1", "=f"(result));
Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.
MSA registers (including control registers) are supported in clobber lists.
llvm-svn: 194476
This commit is contained in:
Daniel Sanders
parent
7c30260ab3
commit
8b59af15ed
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@ -4916,7 +4916,7 @@ public:
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}
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virtual void getGCCRegNames(const char * const *&Names,
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unsigned &NumNames) const {
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static const char * const GCCRegNames[] = {
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static const char *const GCCRegNames[] = {
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// CPU register names
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// Must match second column of GCCRegAliases
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
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@ -4930,7 +4930,15 @@ public:
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
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// Hi/lo and condition register names
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"$fcc5","$fcc6","$fcc7"
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"$fcc5","$fcc6","$fcc7",
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// MSA register names
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"$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7",
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"$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
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"$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
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"$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
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// MSA control register names
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"$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
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"$msarequest", "$msamap", "$msaunmap"
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};
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Names = GCCRegNames;
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NumNames = llvm::array_lengthof(GCCRegNames);
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@ -7,6 +7,8 @@
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Includes:
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- GPR
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- FPU
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- MSA
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Any bad names will make the frontend choke.
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*/
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@ -113,4 +115,36 @@ main()
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__asm__ __volatile__ ("fadd.s $f30,77":::"$f30");
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__asm__ __volatile__ ("fadd.s $f31,77":::"$f31");
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__asm__ __volatile__ ("ldi.w $w0,77":::"$w0");
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__asm__ __volatile__ ("ldi.w $w1,77":::"$w1");
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__asm__ __volatile__ ("ldi.w $w2,77":::"$w2");
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__asm__ __volatile__ ("ldi.w $w3,77":::"$w3");
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__asm__ __volatile__ ("ldi.w $w4,77":::"$w4");
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__asm__ __volatile__ ("ldi.w $w5,77":::"$w5");
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__asm__ __volatile__ ("ldi.w $w6,77":::"$w6");
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__asm__ __volatile__ ("ldi.w $w7,77":::"$w7");
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__asm__ __volatile__ ("ldi.w $w8,77":::"$w8");
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__asm__ __volatile__ ("ldi.w $w9,77":::"$w9");
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__asm__ __volatile__ ("ldi.w $w10,77":::"$w10");
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__asm__ __volatile__ ("ldi.w $w11,77":::"$w10");
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__asm__ __volatile__ ("ldi.w $w12,77":::"$w12");
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__asm__ __volatile__ ("ldi.w $w13,77":::"$w13");
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__asm__ __volatile__ ("ldi.w $w14,77":::"$w14");
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__asm__ __volatile__ ("ldi.w $w15,77":::"$w15");
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__asm__ __volatile__ ("ldi.w $w16,77":::"$w16");
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__asm__ __volatile__ ("ldi.w $w17,77":::"$w17");
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__asm__ __volatile__ ("ldi.w $w18,77":::"$w18");
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__asm__ __volatile__ ("ldi.w $w19,77":::"$w19");
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__asm__ __volatile__ ("ldi.w $w20,77":::"$w20");
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__asm__ __volatile__ ("ldi.w $w21,77":::"$w21");
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__asm__ __volatile__ ("ldi.w $w22,77":::"$w22");
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__asm__ __volatile__ ("ldi.w $w23,77":::"$w23");
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__asm__ __volatile__ ("ldi.w $w24,77":::"$w24");
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__asm__ __volatile__ ("ldi.w $w25,77":::"$w25");
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__asm__ __volatile__ ("ldi.w $w26,77":::"$w26");
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__asm__ __volatile__ ("ldi.w $w27,77":::"$w27");
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__asm__ __volatile__ ("ldi.w $w28,77":::"$w28");
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__asm__ __volatile__ ("ldi.w $w29,77":::"$w29");
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__asm__ __volatile__ ("ldi.w $w30,77":::"$w30");
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__asm__ __volatile__ ("ldi.w $w31,77":::"$w31");
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}
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@ -5,12 +5,16 @@
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int printf(const char*, ...);
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typedef int v4i32 __attribute__((vector_size(16)));
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// CHECK: %{{[0-9]+}} = call i32 asm ".set noreorder;\0Alw $0,$1;\0A.set reorder;\0A", "=r,*m"(i32* getelementptr inbounds ([8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2,
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// CHECK: %{{[0-9]+}} = call i32 asm "lw $0,${1:D};\0A", "=r,*m"(i32* getelementptr inbounds ([8 x i32]* @b, i32 {{[0-9]+}}, i32 {{[0-9]+}})) #2,
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// CHECK: %{{[0-9]+}} = call <4 x i32> asm "ldi.w ${0:w},1", "=f"
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int b[8] = {0,1,2,3,4,5,6,7};
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int main()
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{
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int i;
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v4i32 v4i32_r;
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// The first word. Notice, no 'D'
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{asm (
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@ -29,6 +33,9 @@ int main()
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: "m" (*(b+4))
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);}
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// MSA registers
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{asm ("ldi.w %w0,1" : "=f" (v4i32_r));}
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printf("%d\n",i);
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return 1;
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@ -461,6 +461,11 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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return false;
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}
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}
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case 'w':
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// Print MSA registers for the 'f' constraint
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// In LLVM, the 'w' modifier doesn't need to do anything.
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// We can just call printOperand as normal.
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break;
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}
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}
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@ -20,6 +20,7 @@
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#include "MipsTargetMachine.h"
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#include "MipsTargetObjectFile.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -2777,7 +2778,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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MipsTargetLowering::ConstraintType MipsTargetLowering::
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getConstraintType(const std::string &Constraint) const
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{
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// Mips specific constrainy
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// Mips specific constraints
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// GCC config/mips/constraints.md
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//
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// 'd' : An address register. Equivalent to r
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@ -2828,16 +2829,19 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
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if (type->isIntegerTy())
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weight = CW_Register;
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break;
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case 'f':
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if (type->isFloatTy())
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case 'f': // FPU or MSA register
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if (Subtarget->hasMSA() && type->isVectorTy() &&
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cast<VectorType>(type)->getBitWidth() == 128)
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weight = CW_Register;
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else if (type->isFloatTy())
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weight = CW_Register;
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break;
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case 'c': // $25 for indirect jumps
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case 'l': // lo register
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case 'x': // hilo register pair
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if (type->isIntegerTy())
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if (type->isIntegerTy())
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weight = CW_SpecificReg;
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break;
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break;
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case 'I': // signed 16 bit immediate
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case 'J': // integer zero
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case 'K': // unsigned 16 bit immediate
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@ -2900,6 +2904,29 @@ parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
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RC = TRI->getRegClass(Prefix == "hi" ?
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Mips::HI32RegClassID : Mips::LO32RegClassID);
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return std::make_pair(*(RC->begin()), RC);
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} else if (Prefix.compare(0, 4, "$msa") == 0) {
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// Parse $msa(ir|csr|access|save|modify|request|map|unmap)
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// No numeric characters follow the name.
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if (R.second)
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return std::make_pair((unsigned)0, (const TargetRegisterClass *)0);
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Reg = StringSwitch<unsigned long long>(Prefix)
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.Case("$msair", Mips::MSAIR)
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.Case("$msacsr", Mips::MSACSR)
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.Case("$msaaccess", Mips::MSAAccess)
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.Case("$msasave", Mips::MSASave)
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.Case("$msamodify", Mips::MSAModify)
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.Case("$msarequest", Mips::MSARequest)
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.Case("$msamap", Mips::MSAMap)
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.Case("$msaunmap", Mips::MSAUnmap)
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.Default(0);
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if (!Reg)
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return std::make_pair((unsigned)0, (const TargetRegisterClass *)0);
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RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
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return std::make_pair(Reg, RC);
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}
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if (!R.second)
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@ -2917,8 +2944,10 @@ parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const {
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assert(Reg % 2 == 0);
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Reg >>= 1;
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}
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} else if (Prefix == "$fcc") { // Parse $fcc0-$fcc7.
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} else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
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RC = TRI->getRegClass(Mips::FCCRegClassID);
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else if (Prefix == "$w") { // Parse $w0-$w31.
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RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
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} else { // Parse $0-$31.
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assert(Prefix == "$");
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RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
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@ -2950,10 +2979,18 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const
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return std::make_pair(0U, &Mips::GPR64RegClass);
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// This will generate an error message
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return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
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case 'f':
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if (VT == MVT::f32)
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case 'f': // FPU or MSA register
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if (VT == MVT::v16i8)
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return std::make_pair(0U, &Mips::MSA128BRegClass);
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else if (VT == MVT::v8i16 || VT == MVT::v8f16)
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return std::make_pair(0U, &Mips::MSA128HRegClass);
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else if (VT == MVT::v4i32 || VT == MVT::v4f32)
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return std::make_pair(0U, &Mips::MSA128WRegClass);
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else if (VT == MVT::v2i64 || VT == MVT::v2f64)
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return std::make_pair(0U, &Mips::MSA128DRegClass);
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else if (VT == MVT::f32)
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return std::make_pair(0U, &Mips::FGR32RegClass);
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if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
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else if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
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if (Subtarget->isFP64bit())
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return std::make_pair(0U, &Mips::FGR64RegClass);
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return std::make_pair(0U, &Mips::AFGR64RegClass);
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@ -0,0 +1,34 @@
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; A basic inline assembly test
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; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
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@v4i32_r = global <4 x i32> zeroinitializer, align 16
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define void @test1() nounwind {
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entry:
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; CHECK-LABEL: test1:
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%0 = call <4 x i32> asm "ldi.w ${0:w}, 1", "=f"()
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; CHECK: ldi.w $w{{[1-3]?[0-9]}}, 1
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store <4 x i32> %0, <4 x i32>* @v4i32_r
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ret void
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}
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define void @test2() nounwind {
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entry:
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; CHECK-LABEL: test2:
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%0 = load <4 x i32>* @v4i32_r
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%1 = call <4 x i32> asm "addvi.w ${0:w}, ${1:w}, 1", "=f,f"(<4 x i32> %0)
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; CHECK: addvi.w $w{{[1-3]?[0-9]}}, $w{{[1-3]?[0-9]}}, 1
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store <4 x i32> %1, <4 x i32>* @v4i32_r
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ret void
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}
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define void @test3() nounwind {
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entry:
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; CHECK-LABEL: test3:
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%0 = load <4 x i32>* @v4i32_r
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%1 = call <4 x i32> asm sideeffect "addvi.w ${0:w}, ${1:w}, 1", "=f,f,~{$w0}"(<4 x i32> %0)
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; CHECK: addvi.w $w{{([1-9]|[1-3][0-9])}}, $w{{([1-9]|[1-3][0-9])}}, 1
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store <4 x i32> %1, <4 x i32>* @v4i32_r
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ret void
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}
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