forked from OSchip/llvm-project
parent
aa23fa9f43
commit
8b40cde148
llvm/lib/Target/X86
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@ -2406,14 +2406,6 @@ def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
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[(store FR64:$src, addr:$dst)]>,
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Requires<[HasSSE2]>, XD;
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def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint FR64:$src))]>,
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Requires<[HasSSE2]>, XD;
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def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
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"cvttss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint FR32:$src))]>,
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@ -2422,14 +2414,14 @@ def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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"cvttss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>,
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Requires<[HasSSE1]>, XS;
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def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))]>,
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Requires<[HasSSE2]>, XS;
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def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XS;
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def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint FR64:$src))]>,
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Requires<[HasSSE2]>, XD;
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def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
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"cvtss2sd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend FR32:$src))]>,
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@ -2438,6 +2430,14 @@ def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
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"cvtss2sd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fextend (loadf32 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround FR64:$src))]>,
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Requires<[HasSSE2]>, XS;
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def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
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"cvtsd2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fround (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XS;
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def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
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"cvtsi2ss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (sint_to_fp R32:$src))]>,
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@ -2455,31 +2455,23 @@ def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
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[(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def SQRTSSrm : I<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
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"sqrtss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>,
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Requires<[HasSSE1]>, XS;
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def SQRTSSrr : I<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
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"sqrtss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fsqrt FR32:$src))]>,
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Requires<[HasSSE1]>, XS;
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def SQRTSDrm : I<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
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"sqrtsd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def SQRTSSrm : I<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
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"sqrtss {$src, $dst|$dst, $src}",
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[(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>,
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Requires<[HasSSE1]>, XS;
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def SQRTSDrr : I<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
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"sqrtsd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fsqrt FR64:$src))]>,
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Requires<[HasSSE2]>, XD;
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def SQRTSDrm : I<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
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"sqrtsd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>,
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Requires<[HasSSE2]>, XD;
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def UCOMISDrr: I<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86cmp FR64:$src1, FR64:$src2)]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def UCOMISDrm: I<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86cmp FR64:$src1, (loadf64 addr:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def UCOMISSrr: I<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
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"ucomiss {$src2, $src1|$src1, $src2}",
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[(X86cmp FR32:$src1, FR32:$src2)]>,
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@ -2488,6 +2480,14 @@ def UCOMISSrm: I<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
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"ucomiss {$src2, $src1|$src1, $src2}",
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[(X86cmp FR32:$src1, (loadf32 addr:$src2))]>,
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Requires<[HasSSE1]>, TB;
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def UCOMISDrr: I<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86cmp FR64:$src1, FR64:$src2)]>,
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Requires<[HasSSE2]>, TB, OpSize;
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def UCOMISDrm: I<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
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"ucomisd {$src2, $src1|$src1, $src2}",
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[(X86cmp FR64:$src1, (loadf64 addr:$src2))]>,
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Requires<[HasSSE2]>, TB, OpSize;
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// Pseudo-instructions that map fld0 to xorps/xorpd for sse.
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// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
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@ -2570,7 +2570,25 @@ def SUBSDrm : I<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
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[(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>,
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Requires<[HasSSE2]>, XD;
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// SSE Logical
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// SSE compare
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def CMPSSrr : I<0xC2, MRMSrcReg,
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(ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def CMPSSrm : I<0xC2, MRMSrcMem,
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(ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def CMPSDrr : I<0xC2, MRMSrcReg,
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(ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
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"cmp${cc}sd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XD;
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def CMPSDrm : I<0xC2, MRMSrcMem,
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(ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
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"cmp${cc}sd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE2]>, XD;
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// SSE Logical - these all operate on packed values
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let isCommutable = 1 in {
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def ANDPSrr : I<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
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"andps {$src2, $dst|$dst, $src2}",
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@ -2634,23 +2652,6 @@ def ANDNPDrr : I<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
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def ANDNPDrm : I<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
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"andnpd {$src2, $dst|$dst, $src2}", []>,
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Requires<[HasSSE2]>, TB, OpSize;
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def CMPSSrr : I<0xC2, MRMSrcReg,
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(ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def CMPSSrm : I<0xC2, MRMSrcMem,
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(ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
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"cmp${cc}ss {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XS;
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def CMPSDrr : I<0xC2, MRMSrcReg,
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(ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
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"cmp${cc}sd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE1]>, XD;
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def CMPSDrm : I<0xC2, MRMSrcMem,
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(ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
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"cmp${cc}sd {$src, $dst|$dst, $src}", []>,
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Requires<[HasSSE2]>, XD;
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}
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//===----------------------------------------------------------------------===//
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