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[X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. There is no handling for them. 

llvm-svn: 225344
This commit is contained in:
Craig Topper 2015-01-07 08:10:36 +00:00
parent 23fa478709
commit 8b3c47ca57
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/Target/X86/X86InstrShiftRotate.td
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@ -49,6 +49,7 @@ def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
"shl{q}\t{$src2, $dst|$dst, $src2}", "shl{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))], [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
IIC_SR>; IIC_SR>;
} // isConvertibleToThreeAddress = 1
// NOTE: We don't include patterns for shifts of a register by one, because // NOTE: We don't include patterns for shifts of a register by one, because
// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one). // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
@ -62,7 +63,6 @@ def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
"shl{q}\t$dst", [], IIC_SR>; "shl{q}\t$dst", [], IIC_SR>;
} // hasSideEffects = 0 } // hasSideEffects = 0
} // isConvertibleToThreeAddress = 1
} // Constraints = "$src = $dst", SchedRW } // Constraints = "$src = $dst", SchedRW