forked from OSchip/llvm-project
[X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. There is no handling for them.
llvm-svn: 225344
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@ -49,6 +49,7 @@ def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
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"shl{q}\t{$src2, $dst|$dst, $src2}",
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[(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
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IIC_SR>;
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} // isConvertibleToThreeAddress = 1
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// NOTE: We don't include patterns for shifts of a register by one, because
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// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
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@ -62,7 +63,6 @@ def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
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def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
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"shl{q}\t$dst", [], IIC_SR>;
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} // hasSideEffects = 0
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} // isConvertibleToThreeAddress = 1
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} // Constraints = "$src = $dst", SchedRW
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