forked from OSchip/llvm-project
[NFC][PowerPC] Refactor the tryAndWithMask()
Split the tryAndWithMask into several small calls. Differential Revision: https://reviews.llvm.org/D72250
This commit is contained in:
QingShan Zhang
parent
bae33a7c5a
commit
8b3a62dc98
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@ -204,7 +204,6 @@ namespace {
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bool tryBitfieldInsert(SDNode *N);
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bool tryBitPermutation(SDNode *N);
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bool tryIntCompareInGPR(SDNode *N);
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bool tryAndWithMask(SDNode *N);
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// tryTLSXFormLoad - Convert an ISD::LOAD fed by a PPCISD::ADD_TLS into
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// an X-Form load instruction with the offset being a relocation coming from
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@ -343,6 +342,11 @@ namespace {
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private:
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bool trySETCC(SDNode *N);
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bool tryAsSingleRLDICL(SDNode *N);
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bool tryAsSingleRLDICR(SDNode *N);
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bool tryAsSingleRLWINM(SDNode *N);
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bool tryAsSingleRLWINM8(SDNode *N);
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bool tryAsSingleRLWIMI(SDNode *N);
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void PeepholePPC64();
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void PeepholePPC64ZExt();
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@ -4371,142 +4375,172 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
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return true;
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}
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bool PPCDAGToDAGISel::tryAndWithMask(SDNode *N) {
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if (N->getOpcode() != ISD::AND)
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bool PPCDAGToDAGISel::tryAsSingleRLWINM(SDNode *N) {
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assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
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unsigned Imm;
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if (!isInt32Immediate(N->getOperand(1), Imm))
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return false;
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SDLoc dl(N);
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SDValue Val = N->getOperand(0);
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unsigned Imm, Imm2, SH, MB, ME;
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uint64_t Imm64;
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unsigned SH, MB, ME;
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// If this is an and of a value rotated between 0 and 31 bits and then and'd
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// with a mask, emit rlwinm
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if (isInt32Immediate(N->getOperand(1), Imm) &&
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isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
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SDValue Val = N->getOperand(0).getOperand(0);
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SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
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getI32Imm(ME, dl) };
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if (isRotateAndMask(Val.getNode(), Imm, false, SH, MB, ME)) {
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Val = Val.getOperand(0);
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SDValue Ops[] = {Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
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getI32Imm(ME, dl)};
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
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return true;
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}
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// If this is just a masked value where the input is not handled, and
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// is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
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if (isInt32Immediate(N->getOperand(1), Imm)) {
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if (isRunOfOnes(Imm, MB, ME) &&
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N->getOperand(0).getOpcode() != ISD::ROTL) {
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SDValue Ops[] = { Val, getI32Imm(0, dl), getI32Imm(MB, dl),
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getI32Imm(ME, dl) };
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
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return true;
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}
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// AND X, 0 -> 0, not "rlwinm 32".
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if (Imm == 0) {
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ReplaceUses(SDValue(N, 0), N->getOperand(1));
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return true;
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}
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if (isRunOfOnes(Imm, MB, ME) && Val.getOpcode() != ISD::ROTL) {
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SDValue Ops[] = {Val, getI32Imm(0, dl), getI32Imm(MB, dl),
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getI32Imm(ME, dl)};
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
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return true;
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}
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// ISD::OR doesn't get all the bitfield insertion fun.
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// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
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// bitfield insert.
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if (N->getOperand(0).getOpcode() == ISD::OR &&
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isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
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// The idea here is to check whether this is equivalent to:
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// (c1 & m) | (x & ~m)
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// where m is a run-of-ones mask. The logic here is that, for each bit in
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// c1 and c2:
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// - if both are 1, then the output will be 1.
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// - if both are 0, then the output will be 0.
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// - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
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// come from x.
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// - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
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// be 0.
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// If that last condition is never the case, then we can form m from the
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// bits that are the same between c1 and c2.
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unsigned MB, ME;
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if (isRunOfOnes(~(Imm^Imm2), MB, ME) && !(~Imm & Imm2)) {
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SDValue Ops[] = { N->getOperand(0).getOperand(0),
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N->getOperand(0).getOperand(1),
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getI32Imm(0, dl), getI32Imm(MB, dl),
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getI32Imm(ME, dl) };
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ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
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return true;
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}
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}
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} else if (isInt64Immediate(N->getOperand(1).getNode(), Imm64)) {
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// If this is a 64-bit zero-extension mask, emit rldicl.
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if (isMask_64(Imm64)) {
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MB = 64 - countTrailingOnes(Imm64);
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SH = 0;
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if (Val.getOpcode() == ISD::ANY_EXTEND) {
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auto Op0 = Val.getOperand(0);
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if ( Op0.getOpcode() == ISD::SRL &&
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isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
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auto ResultType = Val.getNode()->getValueType(0);
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auto ImDef = CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl,
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ResultType);
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SDValue IDVal (ImDef, 0);
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Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl,
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ResultType, IDVal, Op0.getOperand(0),
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getI32Imm(1, dl)), 0);
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SH = 64 - Imm;
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}
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}
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// If the operand is a logical right shift, we can fold it into this
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// instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
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// for n <= mb. The right shift is really a left rotate followed by a
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// mask, and this mask is a more-restrictive sub-mask of the mask implied
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// by the shift.
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if (Val.getOpcode() == ISD::SRL &&
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isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
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assert(Imm < 64 && "Illegal shift amount");
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Val = Val.getOperand(0);
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SH = 64 - Imm;
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}
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SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
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CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
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return true;
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} else if (isMask_64(~Imm64)) {
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// If this is a negated 64-bit zero-extension mask,
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// i.e. the immediate is a sequence of ones from most significant side
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// and all zero for reminder, we should use rldicr.
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MB = 63 - countTrailingOnes(~Imm64);
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SH = 0;
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SDValue Ops[] = { Val, getI32Imm(SH, dl), getI32Imm(MB, dl) };
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CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
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return true;
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}
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// It is not 16-bit imm that means we need two instructions at least if
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// using "and" instruction. Try to exploit it with rotate mask instructions.
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if (isRunOfOnes64(Imm64, MB, ME)) {
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if (MB >= 32 && MB <= ME) {
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// MB ME
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// +----------------------+
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// |xxxxxxxxxxx00011111000|
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// +----------------------+
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// 0 32 64
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// We can only do it if the MB is larger than 32 and MB <= ME
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// as RLWINM will replace the content of [0 - 32) with [32 - 64) even
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// we didn't rotate it.
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SDValue Ops[] = { Val, getI64Imm(0, dl), getI64Imm(MB - 32, dl),
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getI64Imm(ME - 32, dl) };
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CurDAG->SelectNodeTo(N, PPC::RLWINM8, MVT::i64, Ops);
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return true;
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}
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// TODO - handle it with rldicl + rldicl
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}
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// AND X, 0 -> 0, not "rlwinm 32".
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if (Imm == 0) {
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ReplaceUses(SDValue(N, 0), N->getOperand(1));
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return true;
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}
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return false;
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}
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bool PPCDAGToDAGISel::tryAsSingleRLWINM8(SDNode *N) {
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assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
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uint64_t Imm64;
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if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64))
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return false;
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unsigned MB, ME;
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if (isRunOfOnes64(Imm64, MB, ME) && MB >= 32 && MB <= ME) {
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// MB ME
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// +----------------------+
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// |xxxxxxxxxxx00011111000|
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// +----------------------+
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// 0 32 64
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// We can only do it if the MB is larger than 32 and MB <= ME
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// as RLWINM will replace the contents of [0 - 32) with [32 - 64) even
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// we didn't rotate it.
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SDLoc dl(N);
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SDValue Ops[] = {N->getOperand(0), getI64Imm(0, dl), getI64Imm(MB - 32, dl),
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getI64Imm(ME - 32, dl)};
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CurDAG->SelectNodeTo(N, PPC::RLWINM8, MVT::i64, Ops);
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return true;
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}
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return false;
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}
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bool PPCDAGToDAGISel::tryAsSingleRLWIMI(SDNode *N) {
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assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
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unsigned Imm;
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if (!isInt32Immediate(N->getOperand(1), Imm))
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return false;
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SDValue Val = N->getOperand(0);
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unsigned Imm2;
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// ISD::OR doesn't get all the bitfield insertion fun.
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// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
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// bitfield insert.
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if (Val.getOpcode() != ISD::OR || !isInt32Immediate(Val.getOperand(1), Imm2))
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return false;
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// The idea here is to check whether this is equivalent to:
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// (c1 & m) | (x & ~m)
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// where m is a run-of-ones mask. The logic here is that, for each bit in
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// c1 and c2:
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// - if both are 1, then the output will be 1.
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// - if both are 0, then the output will be 0.
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// - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
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// come from x.
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// - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
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// be 0.
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// If that last condition is never the case, then we can form m from the
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// bits that are the same between c1 and c2.
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unsigned MB, ME;
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if (isRunOfOnes(~(Imm ^ Imm2), MB, ME) && !(~Imm & Imm2)) {
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SDLoc dl(N);
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SDValue Ops[] = {Val.getOperand(0), Val.getOperand(1), getI32Imm(0, dl),
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getI32Imm(MB, dl), getI32Imm(ME, dl)};
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ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
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return true;
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}
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return false;
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}
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bool PPCDAGToDAGISel::tryAsSingleRLDICL(SDNode *N) {
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assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
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uint64_t Imm64;
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if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) || !isMask_64(Imm64))
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return false;
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// If this is a 64-bit zero-extension mask, emit rldicl.
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unsigned MB = 64 - countTrailingOnes(Imm64);
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unsigned SH = 0;
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unsigned Imm;
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SDValue Val = N->getOperand(0);
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SDLoc dl(N);
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if (Val.getOpcode() == ISD::ANY_EXTEND) {
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auto Op0 = Val.getOperand(0);
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if (Op0.getOpcode() == ISD::SRL &&
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isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
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auto ResultType = Val.getNode()->getValueType(0);
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auto ImDef = CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, ResultType);
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SDValue IDVal(ImDef, 0);
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Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, ResultType,
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IDVal, Op0.getOperand(0),
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getI32Imm(1, dl)),
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0);
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SH = 64 - Imm;
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}
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}
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// If the operand is a logical right shift, we can fold it into this
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// instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
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// for n <= mb. The right shift is really a left rotate followed by a
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// mask, and this mask is a more-restrictive sub-mask of the mask implied
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// by the shift.
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if (Val.getOpcode() == ISD::SRL &&
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isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
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assert(Imm < 64 && "Illegal shift amount");
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Val = Val.getOperand(0);
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SH = 64 - Imm;
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}
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SDValue Ops[] = {Val, getI32Imm(SH, dl), getI32Imm(MB, dl)};
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CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
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return true;
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}
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bool PPCDAGToDAGISel::tryAsSingleRLDICR(SDNode *N) {
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assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
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uint64_t Imm64;
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if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) ||
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!isMask_64(~Imm64))
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return false;
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// If this is a negated 64-bit zero-extension mask,
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// i.e. the immediate is a sequence of ones from most significant side
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// and all zero for reminder, we should use rldicr.
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unsigned MB = 63 - countTrailingOnes(~Imm64);
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unsigned SH = 0;
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SDLoc dl(N);
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SDValue Ops[] = {N->getOperand(0), getI32Imm(SH, dl), getI32Imm(MB, dl)};
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CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
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return true;
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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void PPCDAGToDAGISel::Select(SDNode *N) {
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@ -4730,7 +4764,8 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
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case ISD::AND:
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// If this is an 'and' with a mask, try to emit rlwinm/rldicl/rldicr
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if (tryAndWithMask(N))
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if (tryAsSingleRLWINM(N) || tryAsSingleRLWIMI(N) || tryAsSingleRLDICL(N) ||
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tryAsSingleRLDICR(N) || tryAsSingleRLWINM8(N))
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return;
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// Other cases are autogenerated.
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