forked from OSchip/llvm-project
AMDGPU/GlobalISel: Implement select for G_ICMP and G_SELECT
Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60640 llvm-svn: 363576
This commit is contained in:
Tom Stellard
parent
a8dcd47688
commit
8b1c53b528
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@ -59,11 +59,52 @@ AMDGPUInstructionSelector::AMDGPUInstructionSelector(
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const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
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static bool isSCC(unsigned Reg, const MachineRegisterInfo &MRI) {
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if (Reg == AMDGPU::SCC)
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return true;
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return false;
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auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
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const TargetRegisterClass *RC =
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RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
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if (RC)
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return RC->getID() == AMDGPU::SReg_32_XM0RegClassID &&
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MRI.getType(Reg).getSizeInBits() == 1;
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const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
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return RB->getID() == AMDGPU::SCCRegBankID;
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}
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bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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I.setDesc(TII.get(TargetOpcode::COPY));
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// Special case for COPY from the scc register bank. The scc register bank
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// is modeled using 32-bit sgprs.
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const MachineOperand &Src = I.getOperand(1);
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unsigned SrcReg = Src.getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(SrcReg) && isSCC(SrcReg, MRI)) {
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unsigned DstReg = TRI.getRegSizeInBits(I.getOperand(0).getReg(), MRI);
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unsigned DstSize = TRI.getRegSizeInBits(DstReg, MRI);
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// We have a copy from a 32-bit to 64-bit register. This happens
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// when we are selecting scc->vcc copies.
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if (DstSize == 64) {
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const DebugLoc &DL = I.getDebugLoc();
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), I.getOperand(0).getReg())
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.addImm(0)
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.addReg(SrcReg);
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if (!MRI.getRegClassOrNull(SrcReg))
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MRI.setRegClass(SrcReg, TRI.getConstrainedRegClassForOperand(Src, MRI));
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I.eraseFromParent();
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return true;
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}
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}
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for (const MachineOperand &MO : I.operands()) {
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if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
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continue;
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@ -262,6 +303,101 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I,
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return false;
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}
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static unsigned getV_CMPOpcode(CmpInst::Predicate P, unsigned Size) {
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assert(Size == 32 || Size == 64);
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switch (P) {
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default:
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llvm_unreachable("Unknown condition code!");
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case CmpInst::ICMP_NE:
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return Size == 32 ? AMDGPU::V_CMP_NE_U32_e64 : AMDGPU::V_CMP_NE_U64_e64;
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case CmpInst::ICMP_EQ:
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return Size == 32 ? AMDGPU::V_CMP_EQ_U32_e64 : AMDGPU::V_CMP_EQ_U64_e64;
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case CmpInst::ICMP_SGT:
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return Size == 32 ? AMDGPU::V_CMP_GT_I32_e64 : AMDGPU::V_CMP_GT_I64_e64;
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case CmpInst::ICMP_SGE:
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return Size == 32 ? AMDGPU::V_CMP_GE_I32_e64 : AMDGPU::V_CMP_GE_I64_e64;
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case CmpInst::ICMP_SLT:
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return Size == 32 ? AMDGPU::V_CMP_LT_I32_e64 : AMDGPU::V_CMP_LT_I64_e64;
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case CmpInst::ICMP_SLE:
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return Size == 32 ? AMDGPU::V_CMP_LE_I32_e64 : AMDGPU::V_CMP_LE_I64_e64;
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case CmpInst::ICMP_UGT:
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return Size == 32 ? AMDGPU::V_CMP_GT_U32_e64 : AMDGPU::V_CMP_GT_U64_e64;
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case CmpInst::ICMP_UGE:
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return Size == 32 ? AMDGPU::V_CMP_GE_U32_e64 : AMDGPU::V_CMP_GE_U64_e64;
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case CmpInst::ICMP_ULT:
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return Size == 32 ? AMDGPU::V_CMP_LT_U32_e64 : AMDGPU::V_CMP_LT_U64_e64;
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case CmpInst::ICMP_ULE:
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return Size == 32 ? AMDGPU::V_CMP_LE_U32_e64 : AMDGPU::V_CMP_LE_U64_e64;
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}
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}
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static unsigned getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) {
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// FIXME: VI supports 64-bit comparse.
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assert(Size == 32);
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switch (P) {
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default:
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llvm_unreachable("Unknown condition code!");
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case CmpInst::ICMP_NE:
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return AMDGPU::S_CMP_LG_U32;
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case CmpInst::ICMP_EQ:
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return AMDGPU::S_CMP_EQ_U32;
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case CmpInst::ICMP_SGT:
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return AMDGPU::S_CMP_GT_I32;
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case CmpInst::ICMP_SGE:
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return AMDGPU::S_CMP_GE_I32;
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case CmpInst::ICMP_SLT:
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return AMDGPU::S_CMP_LT_I32;
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case CmpInst::ICMP_SLE:
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return AMDGPU::S_CMP_LE_I32;
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case CmpInst::ICMP_UGT:
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return AMDGPU::S_CMP_GT_U32;
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case CmpInst::ICMP_UGE:
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return AMDGPU::S_CMP_GE_U32;
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case CmpInst::ICMP_ULT:
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return AMDGPU::S_CMP_LT_U32;
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case CmpInst::ICMP_ULE:
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return AMDGPU::S_CMP_LE_U32;
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}
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}
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bool AMDGPUInstructionSelector::selectG_ICMP(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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DebugLoc DL = I.getDebugLoc();
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unsigned SrcReg = I.getOperand(2).getReg();
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unsigned Size = RBI.getSizeInBits(SrcReg, MRI, TRI);
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// FIXME: VI supports 64-bit compares.
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assert(Size == 32);
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unsigned CCReg = I.getOperand(0).getReg();
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if (isSCC(CCReg, MRI)) {
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unsigned Opcode = getS_CMPOpcode((CmpInst::Predicate)I.getOperand(1).getPredicate(), Size);
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MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode))
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.add(I.getOperand(2))
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.add(I.getOperand(3));
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MachineInstr *Copy = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), CCReg)
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.addReg(AMDGPU::SCC);
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bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) |
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constrainSelectedInstRegOperands(*Copy, TII, TRI, RBI);
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I.eraseFromParent();
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return Ret;
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}
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assert(Size == 32 || Size == 64);
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unsigned Opcode = getV_CMPOpcode((CmpInst::Predicate)I.getOperand(1).getPredicate(), Size);
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MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode),
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I.getOperand(0).getReg())
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.add(I.getOperand(2))
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.add(I.getOperand(3));
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RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
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AMDGPU::SReg_64RegClass, MRI);
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bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
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I.eraseFromParent();
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return Ret;
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}
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static MachineInstr *
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buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt,
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unsigned Reg0, unsigned Reg1, unsigned Reg2, unsigned Reg3,
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@ -325,6 +461,53 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
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return false;
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}
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bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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const DebugLoc &DL = I.getDebugLoc();
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unsigned DstReg = I.getOperand(0).getReg();
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unsigned Size = RBI.getSizeInBits(DstReg, MRI, TRI);
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assert(Size == 32 || Size == 64);
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const MachineOperand &CCOp = I.getOperand(1);
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unsigned CCReg = CCOp.getReg();
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if (isSCC(CCReg, MRI)) {
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unsigned SelectOpcode = Size == 32 ? AMDGPU::S_CSELECT_B32 :
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AMDGPU::S_CSELECT_B64;
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MachineInstr *CopySCC = BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
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.addReg(CCReg);
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// The generic constrainSelectedInstRegOperands doesn't work for the scc register
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// bank, because it does not cover the register class that we used to represent
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// for it. So we need to manually set the register class here.
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if (!MRI.getRegClassOrNull(CCReg))
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MRI.setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, MRI));
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MachineInstr *Select = BuildMI(*BB, &I, DL, TII.get(SelectOpcode), DstReg)
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.add(I.getOperand(2))
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.add(I.getOperand(3));
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bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) |
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constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI);
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I.eraseFromParent();
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return Ret;
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}
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assert(Size == 32);
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// FIXME: Support 64-bit select
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MachineInstr *Select =
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BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
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.addImm(0)
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.add(I.getOperand(3))
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.addImm(0)
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.add(I.getOperand(2))
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.add(I.getOperand(1));
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bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI);
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I.eraseFromParent();
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return Ret;
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}
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bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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@ -573,10 +756,14 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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return selectG_INTRINSIC(I, CoverageInfo);
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case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
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return selectG_INTRINSIC_W_SIDE_EFFECTS(I, CoverageInfo);
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case TargetOpcode::G_ICMP:
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return selectG_ICMP(I);
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case TargetOpcode::G_LOAD:
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if (selectImpl(I, CoverageInfo))
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return true;
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return selectG_LOAD(I);
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case TargetOpcode::G_SELECT:
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return selectG_SELECT(I);
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case TargetOpcode::G_STORE:
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return selectG_STORE(I);
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}
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@ -72,11 +72,13 @@ private:
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bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const;
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bool selectG_ICMP(MachineInstr &I) const;
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bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
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void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
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SmallVectorImpl<GEPInfo> &AddrInfo) const;
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bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
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bool selectG_LOAD(MachineInstr &I) const;
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bool selectG_SELECT(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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InstructionSelector::ComplexRendererFns
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@ -1688,6 +1688,10 @@ SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
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Size = PowerOf2Ceil(Size);
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switch (Size) {
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case 1:
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if (RB->getID() == AMDGPU::SCCRegBankID)
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return &AMDGPU::SReg_32_XM0RegClass;
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break;
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case 32:
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return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VGPR_32RegClass :
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&AMDGPU::SReg_32_XM0RegClass;
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@ -1710,8 +1714,9 @@ SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
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return RB->getID() == AMDGPU::VGPRRegBankID ? &AMDGPU::VReg_512RegClass :
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&AMDGPU::SReg_512RegClass;
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default:
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llvm_unreachable("not implemented");
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break;
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}
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llvm_unreachable("not implemented");
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}
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unsigned SIRegisterInfo::getVCC() const {
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@ -1,9 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
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--- |
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define amdgpu_kernel void @copy(i32 addrspace(1)* %global0) {ret void}
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...
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---
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name: copy
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@ -22,6 +19,60 @@ body: |
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%0:sgpr(p1) = COPY $sgpr2_sgpr3
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%1:vgpr(p1) = COPY %0
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%2:vgpr(s32) = G_IMPLICIT_DEF
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G_STORE %2, %1 :: (store 4 into %ir.global0)
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G_STORE %2, %1 :: (store 4, addrspace 1)
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...
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---
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name: copy_vcc_scc
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc
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; GCN-LABEL: name: copy_vcc_scc
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; GCN: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%0:vgpr(p1) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s32) = COPY $vgpr3
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%3:scc(s1) = COPY $scc
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%4:vcc(s1) = COPY %3
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%5:vgpr(s32) = G_SELECT %4, %1, %2
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G_STORE %5, %0 :: (store 4, addrspace 1)
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...
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---
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name: copy_vcc_scc_2_uses
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $scc
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; GCN-LABEL: name: copy_vcc_scc_2_uses
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr3
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; GCN: [[COPY3:%[0-9]+]]:sreg_32_xm0 = COPY $scc
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; GCN: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; GCN: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY2]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_]], implicit $exec
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; GCN: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[COPY3]], implicit $exec
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; GCN: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY1]], [[V_CMP_NE_U32_e64_1]], implicit $exec
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; GCN: FLAT_STORE_DWORD [[COPY]], [[V_CNDMASK_B32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%0:vgpr(p1) = COPY $vgpr0_vgpr1
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%1:vgpr(s32) = COPY $vgpr2
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%2:vgpr(s32) = COPY $vgpr3
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%3:scc(s1) = COPY $scc
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%4:vcc(s1) = COPY %3
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%5:vgpr(s32) = G_SELECT %4, %1, %2
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%6:vcc(s1) = COPY %3
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%7:vgpr(s32) = G_SELECT %6, %1, %5
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G_STORE %7, %0 :: (store 4, addrspace 1)
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...
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---
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@ -0,0 +1,309 @@
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
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---
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name: icmp_s_mix
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legalized: true
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regBankSelected: true
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# GCN: name: icmp_s_mix
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# GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
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# GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
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# GCN: [[SGPR2:%[0-9]+]]:sreg_32 = COPY $sgpr2
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# GCN: [[SGPR3:%[0-9]+]]:sreg_32 = COPY $sgpr3
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# GCN: [[SGPR4:%[0-9]+]]:sreg_32 = COPY $sgpr4
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# GCN: [[SGPR5:%[0-9]+]]:sreg_32 = COPY $sgpr5
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||||
# GCN: [[SGPR6:%[0-9]+]]:sreg_32 = COPY $sgpr6
|
||||
# GCN: [[SGPR7:%[0-9]+]]:sreg_32 = COPY $sgpr7
|
||||
# GCN: S_CMP_LG_U32 [[SGPR0]], [[SGPR1]], implicit-def $scc
|
||||
# GCN-NEXT: [[COND0:%[0-9]+]]:sreg_32_xm0 = COPY $scc
|
||||
# GCN: S_CMP_LG_U32 [[SGPR4]], [[SGPR5]], implicit-def $scc
|
||||
# GCN-NEXT: [[COND1:%[0-9]+]]:sreg_32_xm0 = COPY $scc
|
||||
# GCN: $scc = COPY [[COND0]]
|
||||
# GCN-NEXT: S_CSELECT_B32 [[SGPR6]], [[SGPR7]], implicit $scc
|
||||
# GCN: $scc = COPY [[COND1]]
|
||||
# GCN-NEXT: S_CSELECT_B32 [[SGPR2]], [[SGPR3]], implicit $scc
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:sgpr(s32) = COPY $sgpr0
|
||||
%2:sgpr(s32) = COPY $sgpr1
|
||||
%3:sgpr(s32) = COPY $sgpr2
|
||||
%4:sgpr(s32) = COPY $sgpr3
|
||||
%5:sgpr(s32) = COPY $sgpr4
|
||||
%6:sgpr(s32) = COPY $sgpr5
|
||||
%7:sgpr(s32) = COPY $sgpr6
|
||||
%8:sgpr(s32) = COPY $sgpr7
|
||||
%9:scc(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%10:scc(s1) = G_ICMP intpred(ne), %5, %6
|
||||
%11:sgpr(s32) = G_SELECT %9, %7, %8
|
||||
%12:sgpr(s32) = G_SELECT %10, %3, %4
|
||||
%13:vgpr(s32) = COPY %11
|
||||
G_STORE %13, %0 :: (volatile store 4, addrspace 1)
|
||||
%14:vgpr(s32) = COPY %12
|
||||
G_STORE %14, %0 :: (volatile store 4, addrspace 1)
|
||||
|
||||
...
|
||||
---
|
||||
name: icmp_salu
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# GCN-LABEL: name: icmp_salu
|
||||
# GCN: S_CMP_LG_U32
|
||||
# GCN: S_CMP_EQ_U32
|
||||
# GCN: S_CMP_GT_I32
|
||||
# GCN: S_CMP_GE_I32
|
||||
# GCN: S_CMP_LT_I32
|
||||
# GCN: S_CMP_LE_I32
|
||||
# GCN: S_CMP_GT_U32
|
||||
# GCN: S_CMP_GE_U32
|
||||
# GCN: S_CMP_LT_U32
|
||||
# GCN: S_CMP_LE_U32
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1, $sgpr2, $sgpr3
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:sgpr(s32) = COPY $sgpr0
|
||||
%2:sgpr(s32) = COPY $sgpr1
|
||||
%3:sgpr(s32) = COPY $sgpr2
|
||||
%4:sgpr(s32) = COPY $sgpr3
|
||||
%5:scc(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%6:scc(s1) = G_ICMP intpred(eq), %1, %2
|
||||
%7:scc(s1) = G_ICMP intpred(sgt), %1, %2
|
||||
%8:scc(s1) = G_ICMP intpred(sge), %1, %2
|
||||
%9:scc(s1) = G_ICMP intpred(slt), %1, %2
|
||||
%10:scc(s1) = G_ICMP intpred(sle), %1, %2
|
||||
%11:scc(s1) = G_ICMP intpred(ugt), %1, %2
|
||||
%12:scc(s1) = G_ICMP intpred(uge), %1, %2
|
||||
%13:scc(s1) = G_ICMP intpred(ult), %1, %2
|
||||
%14:scc(s1) = G_ICMP intpred(ule), %1, %2
|
||||
%15:sgpr(s32) = G_SELECT %5, %3, %4
|
||||
%16:sgpr(s32) = G_SELECT %6, %3, %4
|
||||
%17:sgpr(s32) = G_SELECT %7, %3, %4
|
||||
%18:sgpr(s32) = G_SELECT %8, %3, %4
|
||||
%19:sgpr(s32) = G_SELECT %9, %3, %4
|
||||
%20:sgpr(s32) = G_SELECT %10, %3, %4
|
||||
%21:sgpr(s32) = G_SELECT %11, %3, %4
|
||||
%22:sgpr(s32) = G_SELECT %12, %3, %4
|
||||
%23:sgpr(s32) = G_SELECT %13, %3, %4
|
||||
%24:sgpr(s32) = G_SELECT %14, %3, %4
|
||||
%25:vgpr(s32) = COPY %15
|
||||
G_STORE %25, %0 :: (volatile store 4, addrspace 1)
|
||||
%26:vgpr(s32) = COPY %16
|
||||
G_STORE %26, %0 :: (volatile store 4, addrspace 1)
|
||||
%27:vgpr(s32) = COPY %17
|
||||
G_STORE %27, %0 :: (volatile store 4, addrspace 1)
|
||||
%28:vgpr(s32) = COPY %18
|
||||
G_STORE %28, %0 :: (volatile store 4, addrspace 1)
|
||||
%29:vgpr(s32) = COPY %19
|
||||
G_STORE %29, %0 :: (volatile store 4, addrspace 1)
|
||||
%30:vgpr(s32) = COPY %20
|
||||
G_STORE %30, %0 :: (volatile store 4, addrspace 1)
|
||||
%31:vgpr(s32) = COPY %21
|
||||
G_STORE %31, %0 :: (volatile store 4, addrspace 1)
|
||||
%32:vgpr(s32) = COPY %22
|
||||
G_STORE %32, %0 :: (volatile store 4, addrspace 1)
|
||||
%33:vgpr(s32) = COPY %23
|
||||
G_STORE %33, %0 :: (volatile store 4, addrspace 1)
|
||||
%34:vgpr(s32) = COPY %24
|
||||
G_STORE %34, %0 :: (volatile store 4, addrspace 1)
|
||||
|
||||
...
|
||||
---
|
||||
name: icmp_v_mix
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# GCN-LABEL: name: icmp_v_mix
|
||||
# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
# GCN: [[VGPR3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
# GCN: [[VGPR4:%[0-9]+]]:vgpr_32 = COPY $vgpr4
|
||||
# GCN: [[VGPR5:%[0-9]+]]:vgpr_32 = COPY $vgpr5
|
||||
# GCN: [[VGPR6:%[0-9]+]]:vgpr_32 = COPY $vgpr6
|
||||
# GCN: [[VGPR7:%[0-9]+]]:vgpr_32 = COPY $vgpr7
|
||||
# GCN: [[VGPR8:%[0-9]+]]:vgpr_32 = COPY $vgpr8
|
||||
# GCN: [[VGPR9:%[0-9]+]]:vgpr_32 = COPY $vgpr9
|
||||
# GCN: [[COND0:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[VGPR2]], [[VGPR3]]
|
||||
# GCN: [[COND1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[VGPR6]], [[VGPR7]]
|
||||
# GCN: V_CNDMASK_B32_e64 0, [[VGPR9]], 0, [[VGPR8]], [[COND0]]
|
||||
# GCN: V_CNDMASK_B32_e64 0, [[VGPR5]], 0, [[VGPR4]], [[COND1]]
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:vgpr(s32) = COPY $vgpr4
|
||||
%4:vgpr(s32) = COPY $vgpr5
|
||||
%5:vgpr(s32) = COPY $vgpr6
|
||||
%6:vgpr(s32) = COPY $vgpr7
|
||||
%7:vgpr(s32) = COPY $vgpr8
|
||||
%8:vgpr(s32) = COPY $vgpr9
|
||||
%9:sgpr(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%10:sgpr(s1) = G_ICMP intpred(ne), %5, %6
|
||||
%11:vgpr(s32) = G_SELECT %9, %7, %8
|
||||
%12:vgpr(s32) = G_SELECT %10, %3, %4
|
||||
G_STORE %11, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %12, %0 :: (volatile store 4, addrspace 1)
|
||||
...
|
||||
---
|
||||
name: icmp_valu
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# GCN-LABEL: name: icmp_valu
|
||||
# GCN: V_CMP_NE_U32_e64
|
||||
# GCN: V_CMP_EQ_U32_e64
|
||||
# GCN: V_CMP_GT_I32_e64
|
||||
# GCN: V_CMP_GE_I32_e64
|
||||
# GCN: V_CMP_LT_I32_e64
|
||||
# GCN: V_CMP_LE_I32_e64
|
||||
# GCN: V_CMP_GT_U32_e64
|
||||
# GCN: V_CMP_GE_U32_e64
|
||||
# GCN: V_CMP_LT_U32_e64
|
||||
# GCN: V_CMP_LE_U32_e64
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:vgpr(s32) = COPY $vgpr4
|
||||
%4:vgpr(s32) = COPY $vgpr5
|
||||
%5:sgpr(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%6:sgpr(s1) = G_ICMP intpred(eq), %1, %2
|
||||
%7:sgpr(s1) = G_ICMP intpred(sgt), %1, %2
|
||||
%8:sgpr(s1) = G_ICMP intpred(sge), %1, %2
|
||||
%9:sgpr(s1) = G_ICMP intpred(slt), %1, %2
|
||||
%10:sgpr(s1) = G_ICMP intpred(sle), %1, %2
|
||||
%11:sgpr(s1) = G_ICMP intpred(ugt), %1, %2
|
||||
%12:sgpr(s1) = G_ICMP intpred(uge), %1, %2
|
||||
%13:sgpr(s1) = G_ICMP intpred(ult), %1, %2
|
||||
%14:sgpr(s1) = G_ICMP intpred(ule), %1, %2
|
||||
%15:vgpr(s32) = G_SELECT %5, %3, %4
|
||||
%16:vgpr(s32) = G_SELECT %6, %3, %4
|
||||
%17:vgpr(s32) = G_SELECT %7, %3, %4
|
||||
%18:vgpr(s32) = G_SELECT %8, %3, %4
|
||||
%19:vgpr(s32) = G_SELECT %9, %3, %4
|
||||
%20:vgpr(s32) = G_SELECT %10, %3, %4
|
||||
%21:vgpr(s32) = G_SELECT %11, %3, %4
|
||||
%22:vgpr(s32) = G_SELECT %12, %3, %4
|
||||
%23:vgpr(s32) = G_SELECT %13, %3, %4
|
||||
%24:vgpr(s32) = G_SELECT %14, %3, %4
|
||||
G_STORE %15, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %16, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %17, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %18, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %19, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %20, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %21, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %22, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %23, %0 :: (volatile store 4, addrspace 1)
|
||||
G_STORE %24, %0 :: (volatile store 4, addrspace 1)
|
||||
...
|
||||
---
|
||||
|
||||
name: icmp_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# GCN-LABEL: name: icmp_vv
|
||||
# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
# GCN: [[VGPR3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
|
||||
# GCN: V_CMP_NE_U32_e64 [[VGPR2]], [[VGPR3]]
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:vgpr(s32) = COPY $vgpr4
|
||||
%4:vgpr(s32) = COPY $vgpr5
|
||||
%5:sgpr(s1) = G_ICMP intpred(ne), %1, %2
|
||||
%6:vgpr(s32) = G_SELECT %5, %3, %4
|
||||
G_STORE %6, %0 :: (store 4, addrspace 1)
|
||||
...
|
||||
---
|
||||
|
||||
name: icmp_vs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# GCN-LABEL: name: icmp_vs
|
||||
# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
# GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
|
||||
# GCN: V_CMP_NE_U32_e64 [[VGPR2]], [[SGPR0]]
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:vgpr(s32) = COPY $vgpr4
|
||||
%4:sgpr(s32) = COPY $sgpr0
|
||||
%5:sgpr(s1) = G_ICMP intpred(ne), %1, %4
|
||||
%6:vgpr(s32) = G_SELECT %5, %2, %3
|
||||
G_STORE %6, %0 :: (store 4, addrspace 1)
|
||||
...
|
||||
---
|
||||
|
||||
name: icmp_sv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# GCN-LABEL: name: icmp_sv
|
||||
# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
# GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
|
||||
# GCN: V_CMP_NE_U32_e64 [[SGPR0]], [[VGPR2]]
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:vgpr(s32) = COPY $vgpr4
|
||||
%4:sgpr(s32) = COPY $sgpr0
|
||||
%5:sgpr(s1) = G_ICMP intpred(ne), %4, %1
|
||||
%6:vgpr(s32) = G_SELECT %5, %2, %3
|
||||
G_STORE %6, %0 :: (store 4, addrspace 1)
|
||||
...
|
||||
---
|
||||
|
||||
name: icmp_or_vcc
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
# GCN-LABEL: name: icmp_or_vcc
|
||||
# GCN: [[VGPR2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
|
||||
# GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
|
||||
# GCN: V_CMP_NE_U32_e64 [[SGPR0]], [[VGPR2]]
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3, $vgpr4, $sgpr0
|
||||
|
||||
%0:vgpr(p1) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s32) = COPY $vgpr2
|
||||
%2:vgpr(s32) = COPY $vgpr3
|
||||
%3:vgpr(s32) = COPY $vgpr4
|
||||
%4:sgpr(s32) = COPY $sgpr0
|
||||
%5:sgpr(s1) = G_ICMP intpred(ne), %4, %1
|
||||
%6:vgpr(s32) = G_SELECT %5, %2, %3
|
||||
G_STORE %6, %0 :: (store 4, addrspace 1)
|
||||
...
|
||||
---
|
||||
Loading…
Reference in New Issue