forked from OSchip/llvm-project
[X86][SSE] Pull out duplicate VSELECT to shuffle mask code. NFCI.
llvm-svn: 338693
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48eba54f18
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@ -9097,6 +9097,28 @@ static SmallVector<int, 64> createTargetShuffleMask(ArrayRef<int> Mask,
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return TargetMask;
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}
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// Attempt to create a shuffle mask from a VSELECT condition mask.
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static bool createShuffleMaskFromVSELECT(SmallVectorImpl<int> &Mask,
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SDValue Cond) {
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if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
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return false;
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unsigned Size = Cond.getValueType().getVectorNumElements();
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Mask.resize(Size, SM_SentinelUndef);
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for (int i = 0; i != (int)Size; ++i) {
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SDValue CondElt = Cond.getOperand(i);
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Mask[i] = i;
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// Arbitrarily choose from the 2nd operand if the select condition element
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// is undef.
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// TODO: Can we do better by matching patterns such as even/odd?
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if (CondElt.isUndef() || isNullConstant(CondElt))
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Mask[i] += Size;
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}
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return true;
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}
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// Check if the shuffle mask is suitable for the AVX vpunpcklwd or vpunpckhwd
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// instructions.
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static bool isUnpackWdShuffleMask(ArrayRef<int> Mask, MVT VT) {
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@ -15135,26 +15157,15 @@ static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
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SDValue Cond = Op.getOperand(0);
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SDValue LHS = Op.getOperand(1);
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SDValue RHS = Op.getOperand(2);
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SDLoc dl(Op);
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MVT VT = Op.getSimpleValueType();
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if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
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return SDValue();
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auto *CondBV = cast<BuildVectorSDNode>(Cond);
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// Only non-legal VSELECTs reach this lowering, convert those into generic
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// shuffles and re-use the shuffle lowering path for blends.
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SmallVector<int, 32> Mask;
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for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
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SDValue CondElt = CondBV->getOperand(i);
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int M = i;
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// We can't map undef to undef here. They have different meanings. Treat
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// as the same as zero.
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if (CondElt.isUndef() || isNullConstant(CondElt))
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M += Size;
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Mask.push_back(M);
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}
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return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
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if (createShuffleMaskFromVSELECT(Mask, Cond))
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return DAG.getVectorShuffle(VT, SDLoc(Op), LHS, RHS, Mask);
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return SDValue();
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}
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SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
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@ -32560,17 +32571,8 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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// Convert vselects with constant condition into shuffles.
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if (ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()) &&
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DCI.isBeforeLegalizeOps()) {
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SmallVector<int, 64> Mask(VT.getVectorNumElements(), -1);
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for (int i = 0, Size = Mask.size(); i != Size; ++i) {
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SDValue CondElt = Cond->getOperand(i);
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Mask[i] = i;
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// Arbitrarily choose from the 2nd operand if the select condition element
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// is undef.
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// TODO: Can we do better by matching patterns such as even/odd?
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if (CondElt.isUndef() || isNullConstant(CondElt))
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Mask[i] += Size;
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}
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SmallVector<int, 64> Mask;
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if (createShuffleMaskFromVSELECT(Mask, Cond))
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return DAG.getVectorShuffle(VT, DL, LHS, RHS, Mask);
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}
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