forked from OSchip/llvm-project
[Power9]Legalize and emit code for W vector extract and convert to QP
Implemente patterns to extract [Un]signed Word vector element and convert to quad-precision. Differential Revision: https://reviews.llvm.org/D46536 llvm-svn: 333115
This commit is contained in:
Lei Huang
parent
b1ba127aa8
commit
8b0da65bfb
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@ -3152,21 +3152,38 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
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(f32 (DFLOADf32 ixaddr:$src))>;
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// (Un)Signed DWord vector extract -> QP
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let Predicates = [IsBigEndian] in {
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def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
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(f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
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def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
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(f128 (XSCVSDQP
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(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
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def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
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(f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
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def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
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(f128 (XSCVUDQP
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(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
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}
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let Predicates = [IsBigEndian, HasP9Vector] in {
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let Predicates = [IsLittleEndian] in {
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// (Un)Signed DWord vector extract -> QP
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def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
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(f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>;
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def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 1)))),
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(f128 (XSCVSDQP
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(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
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def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 0)))),
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(f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
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def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
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(f128 (XSCVUDQP
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(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
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// (Un)Signed Word vector extract -> QP
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def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 1)))),
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(f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
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foreach Idx = [0,2,3] in {
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def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
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(f128 (XSCVSDQP (EXTRACT_SUBREG
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(VEXTSW2D (VSPLTW Idx, $src)), sub_64)))>;
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}
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foreach Idx = 0-3 in {
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def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, Idx)))),
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(f128 (XSCVUDQP (XXEXTRACTUW $src, !shl(Idx, 2))))>;
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}
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} // IsBigEndian, HasP9Vector
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let Predicates = [IsLittleEndian, HasP9Vector] in {
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// (Un)Signed DWord vector extract -> QP
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def : Pat<(f128 (sint_to_fp (i64 (extractelt v2i64:$src, 0)))),
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(f128 (XSCVSDQP
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(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
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@ -3177,7 +3194,22 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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(EXTRACT_SUBREG (XXPERMDI $src, $src, 3), sub_64)))>;
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def : Pat<(f128 (uint_to_fp (i64 (extractelt v2i64:$src, 1)))),
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(f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>;
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}
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// (Un)Signed Word vector extract -> QP
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foreach Idx = [[0,3],[1,2],[3,0]] in {
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def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
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(f128 (XSCVSDQP (EXTRACT_SUBREG
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(VEXTSW2D (VSPLTW !head(!tail(Idx)), $src)),
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sub_64)))>;
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}
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def : Pat<(f128 (sint_to_fp (i32 (extractelt v4i32:$src, 2)))),
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(f128 (XSCVSDQP (EXTRACT_SUBREG (VEXTSW2D $src), sub_64)))>;
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foreach Idx = [[0,12],[1,8],[2,4],[3,0]] in {
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def : Pat<(f128 (uint_to_fp (i32 (extractelt v4i32:$src, !head(Idx))))),
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(f128 (XSCVUDQP (XXEXTRACTUW $src, !head(!tail(Idx)))))>;
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}
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} // IsLittleEndian, HasP9Vector
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// Convert (Un)Signed DWord in memory -> QP
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def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))),
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@ -5,6 +5,8 @@
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; RUN: -verify-machineinstrs -enable-ppc-quad-precision < %s | \
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; RUN: FileCheck %s -check-prefix=CHECK-BE
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; Vector extract DWord and convert to quad precision.
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@sdwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
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@udwVecMem = global <2 x i64> <i64 88, i64 99>, align 16
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@ -158,3 +160,182 @@ entry:
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Vector extract Word and convert to quad precision.
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@swVecMem = global <4 x i32> <i32 88, i32 99, i32 100, i32 2>, align 16
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@uwVecMem = global <4 x i32> <i32 89, i32 89, i32 200, i32 3>, align 16
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vspltw 2, 2, 3
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; CHECK-NEXT: vextsw2d 2, 2
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; CHECK-NEXT: xscvsdqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp:
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; CHECK-BE: vspltw 2, 2, 0
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; CHECK-BE-NEXT: vextsw2d 2, 2
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; CHECK-BE-NEXT: xscvsdqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 0
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vspltw 2, 2, 2
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; CHECK-NEXT: vextsw2d 2, 2
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; CHECK-NEXT: xscvsdqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp1:
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; CHECK-BE: vextsw2d 2, 2
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; CHECK-BE-NEXT: xscvsdqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 1
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vextsw2d 2, 2
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; CHECK-NEXT: xscvsdqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp2:
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; CHECK-BE: vspltw 2, 2, 2
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; CHECK-BE-NEXT: vextsw2d 2, 2
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; CHECK-BE-NEXT: xscvsdqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 2
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @swVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: swVecConv2qp3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vspltw 2, 2, 0
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; CHECK-NEXT: vextsw2d 2, 2
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; CHECK-NEXT: xscvsdqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: swVecConv2qp3:
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; CHECK-BE: vspltw 2, 2, 3
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; CHECK-BE-NEXT: vextsw2d 2, 2
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; CHECK-BE-NEXT: xscvsdqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 3
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%conv = sitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw 34, 34, 12
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; CHECK-NEXT: xscvudqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp:
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; CHECK-BE: xxextractuw 34, 34, 0
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; CHECK-BE-NEXT: xscvudqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 0
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp1(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw 34, 34, 8
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; CHECK-NEXT: xscvudqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp1:
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; CHECK-BE: xxextractuw 34, 34, 4
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; CHECK-BE-NEXT: xscvudqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 1
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp2(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw 34, 34, 4
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; CHECK-NEXT: xscvudqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp2:
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; CHECK-BE: xxextractuw 34, 34, 8
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; CHECK-BE-NEXT: xscvudqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 2
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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; Function Attrs: norecurse nounwind
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define void @uwVecConv2qp3(fp128* nocapture %a, <4 x i32> %b) {
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; CHECK-LABEL: uwVecConv2qp3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxextractuw 34, 34, 0
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; CHECK-NEXT: xscvudqp 2, 2
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; CHECK-NEXT: stxv 34, 0(3)
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; CHECK-NEXT: blr
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; CHECK-BE-LABEL: uwVecConv2qp3:
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; CHECK-BE: xxextractuw 34, 34, 12
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; CHECK-BE-NEXT: xscvudqp 2, 2
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; CHECK-BE-NEXT: stxv 34, 0(3)
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; CHECK-BE-NEXT: blr
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entry:
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%vecext = extractelement <4 x i32> %b, i32 3
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%conv = uitofp i32 %vecext to fp128
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store fp128 %conv, fp128* %a, align 16
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ret void
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}
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