maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[SystemZ] Preserve the MachineMemOperand in emitCondStore() in all cases. 

Review: Ulrich Weigand
This commit is contained in:
Jonas Paulsson 2020-08-24 14:07:30 +02:00
parent 2431b143ae
commit 8ac70694b9
1 changed files with 11 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -7246,6 +7246,15 @@ MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
// ISel pattern matching also adds a load memory operand of the same
// address, so take special care to find the storing memory operand.
MachineMemOperand *MMO = nullptr;
for (auto *I : MI.memoperands())
if (I->isStore()) {
MMO = I;
break;
}
// Use STOCOpcode if possible. We could use different store patterns in
// order to avoid matching the index register, but the performance trade-offs
// might be more complicated in that case.
@ -7253,15 +7262,6 @@ MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
if (Invert)
CCMask ^= CCValid;
// ISel pattern matching also adds a load memory operand of the same
// address, so take special care to find the storing memory operand.
MachineMemOperand *MMO = nullptr;
for (auto *I : MI.memoperands())
if (I->isStore()) {
MMO = I;
break;
}
BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
.addReg(SrcReg)
.add(Base)
@ -7306,7 +7306,8 @@ MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
.addReg(SrcReg)
.add(Base)
.addImm(Disp)
.addReg(IndexReg);
.addReg(IndexReg)
.addMemOperand(MMO);
MBB->addSuccessor(JoinMBB);
MI.eraseFromParent();