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AMDGPU: Mark s_barrier as a high latency instruction 

These were marked as WriteSALU, which is low latency.
I'm guessing at the value to use, but it should probably
be considered the highest latency instruction.

I'm not sure this has any actual effect since hasSideEffects
probably is preventing any moving of these.

llvm-svn: 247060
This commit is contained in:
Matt Arsenault 2015-09-08 19:54:32 +00:00
parent 8fb810a1d2
commit 8ac35cd031
2 changed files with 3 additions and 0 deletions
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1
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -479,6 +479,7 @@ let hasSideEffects = 1 in {
def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
[(int_AMDGPU_barrier_local)]
> {
let SchedRW = [WriteBarrier];
let simm16 = 0;
let mayLoad = 1;
let mayStore = 1;

2
llvm/lib/Target/AMDGPU/SISchedule.td
View File

@ -17,6 +17,7 @@ def WriteLDS : SchedWrite;
def WriteSALU : SchedWrite;
def WriteSMEM : SchedWrite;
def WriteVMEM : SchedWrite;
def WriteBarrier : SchedWrite;
// Vector ALU instructions
def Write32Bit : SchedWrite;
@ -64,6 +65,7 @@ multiclass SICommonWriteRes {
def : HWWriteRes<WriteSALU, [HWSALU], 1>;
def : HWWriteRes<WriteSMEM, [HWLGKM], 10>; // XXX: Guessed ???
def : HWWriteRes<WriteVMEM, [HWVMEM], 450>; // 300 - 600
def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
def : HWVALUWriteRes<Write32Bit, 1>;
def : HWVALUWriteRes<WriteQuarterRate32, 4>;