forked from OSchip/llvm-project
[Inline asm] Fix mangle problem when variable used in inline asm.
(Connect InlineAsm Memory Operand with its real value not just name) Revert 2 history bugfix patch: Revert "[X86][MS-InlineAsm] Make the constraint *m to be simple place holder" This patch revert https://reviews.llvm.org/D115225 which mainly fix problems intrduced by https://reviews.llvm.org/D113096 This reverts commitd7c07f60b3
. Revert "Reland "[X86][MS-InlineAsm] Use exact conditions to recognize MS global variables"" This patch revert https://reviews.llvm.org/D116090 which fix problem intrduced by https://reviews.llvm.org/D115225 This reverts commit24c68ea1eb
. Reviewed By: skan Differential Revision: https://reviews.llvm.org/D120886
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@ -18,4 +18,4 @@ void __attribute__ ((naked)) foo(void)
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}}
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// CHECK-LABEL: foo
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// CHECK: call void asm sideeffect inteldialect "fmul qword ptr static_const_table[edx + $$240]\0A\09ret"
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// CHECK: call void asm sideeffect inteldialect "fmul qword ptr $0[edx + $$240]\0A\09ret"
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@ -5,6 +5,6 @@
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static int arr[10];
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void t1(void) {
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// CHECK: @arr = internal global [10 x i32]
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// CHECK: call void asm sideeffect inteldialect "mov dword ptr arr[edx * $$4],edx", "=*m,{{.*}}([10 x i32]* elementtype([10 x i32]) @arr)
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// CHECK: call void asm sideeffect inteldialect "mov dword ptr $0[edx * $$4],edx", "=*m,{{.*}}([10 x i32]* elementtype([10 x i32]) @arr)
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__asm mov dword ptr arr[edx*4],edx
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}
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@ -2,20 +2,20 @@
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// RUN: %clang_cc1 %s -fasm-blocks -triple i386-apple-darwin10 -emit-llvm -o - | FileCheck %s
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int gVar;
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void t1(void) {
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// CHECK: add eax, dword ptr gVar[eax]
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void t1() {
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// CHECK: add eax, dword ptr ${{[0-9]}}[eax]
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__asm add eax, dword ptr gVar[eax]
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// CHECK: add dword ptr gVar[eax], eax
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// CHECK: add dword ptr ${{[0-9]}}[eax], eax
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__asm add dword ptr [eax+gVar], eax
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// CHECK: add ebx, dword ptr gVar[ebx + $$270]
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// CHECK: add ebx, dword ptr ${{[0-9]}}[ebx + $$270]
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__asm add ebx, dword ptr gVar[271 - 82 + 81 + ebx]
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// CHECK: add dword ptr gVar[ebx + $$828], ebx
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// CHECK: add dword ptr ${{[0-9]}}[ebx + $$828], ebx
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__asm add dword ptr [ebx + gVar + 828], ebx
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// CHECK: add ecx, dword ptr gVar[ecx + ecx * $$4 + $$4590]
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// CHECK: add ecx, dword ptr ${{[0-9]}}[ecx + ecx * $$4 + $$4590]
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__asm add ecx, dword ptr gVar[4590 + ecx + ecx*4]
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// CHECK: add dword ptr gVar[ecx + ecx * $$8 + $$73], ecx
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// CHECK: add dword ptr ${{[0-9]}}[ecx + ecx * $$8 + $$73], ecx
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__asm add dword ptr [gVar + ecx + 45 + 23 - 53 + 60 - 2 + ecx*8], ecx
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// CHECK: add gVar[ecx + ebx + $$7], eax
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// CHECK: add ${{[0-9]}}[ecx + ebx + $$7], eax
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__asm add 1 + 1 + 2 + 3[gVar + ecx + ebx], eax
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}
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@ -10,7 +10,6 @@
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#define LLVM_MC_MCPARSER_MCPARSEDASMOPERAND_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Support/SMLoc.h"
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#include <string>
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@ -77,10 +76,6 @@ public:
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/// assembly.
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virtual bool isOffsetOfLocal() const { return false; }
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/// isMemPlaceholder - Do we need to ignore the constraint, rather than emit
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/// code? Only valid when parsing MS-style inline assembly.
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virtual bool isMemPlaceholder(const MCInstrDesc &Desc) const { return false; }
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/// getOffsetOfLoc - Get the location of the offset operator.
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virtual SMLoc getOffsetOfLoc() const { return SMLoc(); }
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@ -6022,13 +6022,12 @@ bool AsmParser::parseMSInlineAsm(
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bool isOutput = (i == 1) && Desc.mayStore();
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SMLoc Start = SMLoc::getFromPointer(SymName.data());
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int64_t Size = Operand.isMemPlaceholder(Desc) ? 0 : SymName.size();
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if (isOutput) {
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++InputIdx;
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OutputDecls.push_back(OpDecl);
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OutputDeclsAddressOf.push_back(Operand.needAddressOf());
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OutputConstraints.push_back(("=" + Constraint).str());
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AsmStrRewrites.emplace_back(AOK_Output, Start, Size);
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AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size());
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} else {
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InputDecls.push_back(OpDecl);
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InputDeclsAddressOf.push_back(Operand.needAddressOf());
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@ -6036,7 +6035,7 @@ bool AsmParser::parseMSInlineAsm(
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if (Desc.OpInfo[i - 1].isBranchTarget())
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AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size());
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else
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AsmStrRewrites.emplace_back(AOK_Input, Start, Size);
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AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size());
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}
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}
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@ -6151,17 +6150,13 @@ bool AsmParser::parseMSInlineAsm(
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OS << Ctx.getAsmInfo()->getPrivateLabelPrefix() << AR.Label;
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break;
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case AOK_Input:
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if (AR.Len)
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OS << '$' << InputIdx;
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++InputIdx;
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OS << '$' << InputIdx++;
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break;
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case AOK_CallInput:
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OS << "${" << InputIdx++ << ":P}";
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break;
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case AOK_Output:
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if (AR.Len)
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OS << '$' << OutputIdx;
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++OutputIdx;
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OS << '$' << OutputIdx++;
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break;
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case AOK_SizeDirective:
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switch (AR.Val) {
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@ -1759,8 +1759,7 @@ bool X86AsmParser::CreateMemForMSInlineAsm(
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// registers in a mmory expression, and though unaccessible via rip/eip.
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if (IsGlobalLV && (BaseReg || IndexReg)) {
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Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start,
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End, Size, Identifier, Decl,
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FrontendSize));
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End, Size, Identifier, Decl));
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return false;
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}
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// Otherwise, we set the base register to a non-zero value
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@ -2552,6 +2551,8 @@ bool X86AsmParser::ParseIntelOperand(OperandVector &Operands) {
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StringRef ErrMsg;
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unsigned BaseReg = SM.getBaseReg();
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unsigned IndexReg = SM.getIndexReg();
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if (IndexReg && BaseReg == X86::RIP)
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BaseReg = 0;
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unsigned Scale = SM.getScale();
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if (!PtrInOperand)
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Size = SM.getElementSize() << 3;
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@ -287,12 +287,6 @@ struct X86Operand final : public MCParsedAsmOperand {
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bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; }
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bool isMemPlaceholder(const MCInstrDesc &Desc) const override {
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// Only MS InlineAsm uses global variables with registers rather than
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// rip/eip.
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return isMem() && !Mem.DefaultBaseReg && Mem.FrontendSize;
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}
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bool needAddressOf() const override { return AddressOf; }
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bool isMem() const override { return Kind == Memory; }
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@ -5,7 +5,7 @@
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; CHECK: movl %edx, arr(,%rdx,4)
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define dso_local i32 @main() #0 {
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entry:
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call void asm sideeffect inteldialect "mov dword ptr arr[rdx * $$4],edx", "=*m,~{dirflag},~{fpsr},~{flags}"([10 x i32]* elementtype([10 x i32]) @arr) #1, !srcloc !4
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call void asm sideeffect inteldialect "mov dword ptr $0[rdx * $$4],edx", "=*m,~{dirflag},~{fpsr},~{flags}"([10 x i32]* elementtype([10 x i32]) @arr) #1, !srcloc !4
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ret i32 0
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}
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