forked from OSchip/llvm-project
AMDGPU: Change how exp is printed
This is an improvement over a long list of unreadable numbers. A follow up patch will try to match how sc formats these. llvm-svn: 288697
This commit is contained in:
Matt Arsenault
parent
0dd2306538
commit
8a63cb9044
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@ -135,6 +135,8 @@ public:
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ImmTyDA,
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ImmTyR128,
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ImmTyLWE,
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ImmTyExpCompr,
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ImmTyExpVM,
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ImmTyHwreg,
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ImmTySendMsg,
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};
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@ -228,6 +230,8 @@ public:
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bool isDA() const { return isImmTy(ImmTyDA); }
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bool isR128() const { return isImmTy(ImmTyUNorm); }
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bool isLWE() const { return isImmTy(ImmTyLWE); }
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bool isExpVM() const { return isImmTy(ImmTyExpVM); }
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bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }
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bool isOffen() const { return isImmTy(ImmTyOffen); }
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bool isIdxen() const { return isImmTy(ImmTyIdxen); }
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bool isAddr64() const { return isImmTy(ImmTyAddr64); }
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@ -484,6 +488,8 @@ public:
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case ImmTyDA: OS << "DA"; break;
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case ImmTyR128: OS << "R128"; break;
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case ImmTyLWE: OS << "LWE"; break;
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case ImmTyExpCompr: OS << "ExpCompr"; break;
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case ImmTyExpVM: OS << "ExpVM"; break;
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case ImmTyHwreg: OS << "Hwreg"; break;
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case ImmTySendMsg: OS << "SendMsg"; break;
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}
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@ -745,6 +751,8 @@ public:
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AMDGPUOperand::Ptr defaultSMRDOffset8() const;
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AMDGPUOperand::Ptr defaultSMRDOffset20() const;
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AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
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AMDGPUOperand::Ptr defaultExpCompr() const;
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AMDGPUOperand::Ptr defaultExpVM() const;
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OperandMatchResultTy parseOModOperand(OperandVector &Operands);
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@ -2531,6 +2539,14 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultLWE() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyLWE);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpCompr() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpCompr);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultExpVM() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyExpVM);
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}
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//===----------------------------------------------------------------------===//
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// smrd
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//===----------------------------------------------------------------------===//
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@ -195,6 +195,20 @@ void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
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printNamedBit(MI, OpNo, O, "lwe");
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}
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void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " compr";
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}
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void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " vm";
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}
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void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
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const MCRegisterInfo &MRI) {
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switch (RegNo) {
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@ -599,10 +613,72 @@ void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
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}
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}
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void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNo,
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template <unsigned N>
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void AMDGPUInstPrinter::printExpSrcN(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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int EnIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::en);
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unsigned En = MI->getOperand(EnIdx).getImm();
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// FIXME: What do we do with compr? The meaning of en changes depending on if
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// compr is set.
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if (En & (1 << N))
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printRegOperand(MI->getOperand(OpNo).getReg(), O, MRI);
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else
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O << "off";
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}
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void AMDGPUInstPrinter::printExpSrc0(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printExpSrcN<0>(MI, OpNo, STI, O);
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}
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void AMDGPUInstPrinter::printExpSrc1(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printExpSrcN<1>(MI, OpNo, STI, O);
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}
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void AMDGPUInstPrinter::printExpSrc2(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printExpSrcN<2>(MI, OpNo, STI, O);
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}
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void AMDGPUInstPrinter::printExpSrc3(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printExpSrcN<3>(MI, OpNo, STI, O);
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}
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void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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// This is really a 6 bit field.
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uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
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if (Tgt <= 7)
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O << " mrt" << Tgt;
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else if (Tgt == 8)
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O << " mrtz";
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else if (Tgt == 9)
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O << " null";
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else if (Tgt >= 12 && Tgt <= 15)
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O << " pos" << Tgt - 12;
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else if (Tgt >= 32 && Tgt <= 63)
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O << " param" << Tgt - 32;
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else {
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// Reserved values 10, 11
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O << " invalid_target_" << Tgt;
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}
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}
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void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNo).getImm();
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unsigned Imm = MI->getOperand(OpNum).getImm();
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if (Imm == 2) {
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O << "P0";
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@ -78,8 +78,13 @@ private:
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raw_ostream &O);
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void printR128(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printLWE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printLWE(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExpCompr(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExpVM(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printRegOperand(unsigned RegNo, raw_ostream &O);
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void printVOPDst(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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@ -116,6 +121,22 @@ private:
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printMemOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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template <unsigned N>
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void printExpSrcN(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExpSrc0(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExpSrc1(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExpSrc2(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExpSrc3(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printExpTgt(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
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StringRef Asm, StringRef Default = "");
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static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
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@ -385,6 +385,8 @@ def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
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def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
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def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
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def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
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def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
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def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
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def dmask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
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@ -400,6 +402,10 @@ def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused
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def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
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def exp_tgt : Operand<i8> {
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let PrintMethod = "printExpTgt";
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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@ -520,9 +526,10 @@ class SIMCInstr <string pseudo, int subtarget> {
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class EXP_Helper<bit done, SDPatternOperator node = null_frag> : EXPCommon<
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(outs),
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(ins i8imm:$tgt, VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3,
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i1imm:$vm, i1imm:$compr, i8imm:$en),
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"exp $en, $tgt, $compr, "#!if(done, "1", "0")#", $vm, $src0, $src1, $src2, $src3",
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(ins exp_tgt:$tgt,
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ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
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exp_vm:$vm, exp_compr:$compr, i8imm:$en),
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"exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm",
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[(node (i8 timm:$en), (i1 timm:$vm), (i8 timm:$tgt), (i1 timm:$compr),
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f32:$src0, f32:$src1, f32:$src2, f32:$src3)]
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>;
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@ -449,3 +449,24 @@ def VRegSrc_32 : RegisterOperand<VGPR_32> {
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//===----------------------------------------------------------------------===//
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defm VCSrc : RegInlineOperand<"VS", "VCSrc">;
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// ===----------------------------------------------------------------------===//
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// ExpSrc* Special cases for exp src operands which are printed as
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// "off" depending on en operand.
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// ===----------------------------------------------------------------------===//
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def ExpSrc0 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc0";
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}
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def ExpSrc1 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc1";
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}
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def ExpSrc2 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc2";
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}
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def ExpSrc3 : RegisterOperand<VGPR_32> {
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let PrintMethod = "printExpSrc3";
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}
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@ -0,0 +1,237 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) #0
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; GCN-LABEL: {{^}}test_export_zeroes:
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; GCN: exp mrt0 off, off, off, off{{$}}
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; GCN: exp mrt0 off, off, off, off done{{$}}
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define void @test_export_zeroes() #0 {
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call void @llvm.SI.export(i32 0, i32 0, i32 0, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
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call void @llvm.SI.export(i32 0, i32 0, i32 1, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
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ret void
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}
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; FIXME: Should not set up registers for the unused source registers.
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; GCN-LABEL: {{^}}test_export_en_src0:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
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; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
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; GCN: exp mrt0 [[SRC0]], off, off, off done{{$}}
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define void @test_export_en_src0() #0 {
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call void @llvm.SI.export(i32 1, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_en_src1:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
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; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
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; GCN: exp mrt0 off, [[SRC1]], off, off done{{$}}
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define void @test_export_en_src1() #0 {
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call void @llvm.SI.export(i32 2, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_en_src2:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
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; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
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; GCN: exp mrt0 off, off, [[SRC2]], off done{{$}}
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define void @test_export_en_src2() #0 {
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call void @llvm.SI.export(i32 4, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_en_src3:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
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; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
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; GCN: exp mrt0 off, off, off, [[SRC3]] done{{$}}
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define void @test_export_en_src3() #0 {
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call void @llvm.SI.export(i32 8, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_en_src0_src1:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
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; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
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; GCN: exp mrt0 [[SRC0]], [[SRC1]], off, off done{{$}}
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define void @test_export_en_src0_src1() #0 {
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call void @llvm.SI.export(i32 3, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_en_src0_src2:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
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; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
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; GCN: exp mrt0 [[SRC0]], off, [[SRC2]], off done{{$}}
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define void @test_export_en_src0_src2() #0 {
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call void @llvm.SI.export(i32 5, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_en_src0_src3:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
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; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
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; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
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; GCN: exp mrt0 [[SRC0]], off, off, [[SRC3]]{{$}}
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; GCN: exp mrt0 [[SRC0]], off, off, [[SRC3]] done{{$}}
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define void @test_export_en_src0_src3() #0 {
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call void @llvm.SI.export(i32 9, i32 0, i32 0, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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call void @llvm.SI.export(i32 9, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
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ret void
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}
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; GCN-LABEL: {{^}}test_export_en_src0_src1_src2_src3:
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; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
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; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_en_src0_src1_src2_src3() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_mrt7:
|
||||
; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 0.5
|
||||
; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}}
|
||||
; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}}
|
||||
define void @test_export_mrt7() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 7, i32 0, float 0.5, float 0.5, float 0.5, float 0.5)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 7, i32 0, float 0.5, float 0.5, float 0.5, float 0.5)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_z:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_z() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 8, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 8, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_null:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_null() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 9, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 9, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_reserved10:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_reserved10() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 10, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 10, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_reserved11:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_reserved11() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 11, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 11, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_pos0:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_pos0() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 12, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_pos3:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_pos3() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 15, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 15, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_param0:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_param0() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 32, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_param31:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}}
|
||||
; GCN: exp param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}}
|
||||
define void @test_export_param31() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 63, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 63, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}test_export_vm:
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5
|
||||
; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0
|
||||
; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}}
|
||||
; GCN: exp mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}}
|
||||
define void @test_export_vm() #0 {
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 0, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float 1.0, float 2.0, float 0.5, float 4.0)
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "ShaderType"="0" }
|
||||
|
|
@ -6,7 +6,7 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float
|
|||
; GCN-LABEL: {{^}}vgpr:
|
||||
; GCN: v_mov_b32_e32 v1, v0
|
||||
; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
|
||||
; GCN-DAG: exp 15, 0, -1, 1, -1, v1, v1, v1, v1
|
||||
; GCN-DAG: exp mrt0 v1, v1, v1, v1 done compr vm
|
||||
; GCN: s_waitcnt expcnt(0)
|
||||
; GCN-NOT: s_endpgm
|
||||
define amdgpu_vs {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) {
|
||||
|
|
@ -19,7 +19,8 @@ define amdgpu_vs {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 i
|
|||
|
||||
; GCN-LABEL: {{^}}vgpr_literal:
|
||||
; GCN: v_mov_b32_e32 v4, v0
|
||||
; GCN: exp 15, 0, -1, 1, -1, v4, v4, v4, v4
|
||||
; GCN: exp mrt0 v4, v4, v4, v4 done compr vm
|
||||
|
||||
; GCN-DAG: v_mov_b32_e32 v0, 1.0
|
||||
; GCN-DAG: v_mov_b32_e32 v1, 2.0
|
||||
; GCN-DAG: v_mov_b32_e32 v2, 4.0
|
||||
|
|
@ -43,7 +44,6 @@ define amdgpu_vs {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addr
|
|||
; GCN: v_mov_b32_e32 v3, v4
|
||||
; GCN: v_mov_b32_e32 v4, v6
|
||||
; GCN-NOT: s_endpgm
|
||||
attributes #0 = { "InitialPSInputAddr"="0" }
|
||||
define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
|
||||
%i0 = extractelement <2 x i32> %4, i32 0
|
||||
%i1 = extractelement <2 x i32> %4, i32 1
|
||||
|
|
@ -209,7 +209,7 @@ define amdgpu_vs {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)
|
|||
|
||||
; GCN-LABEL: {{^}}both:
|
||||
; GCN: v_mov_b32_e32 v1, v0
|
||||
; GCN-DAG: exp 15, 0, -1, 1, -1, v1, v1, v1, v1
|
||||
; GCN-DAG: exp mrt0 v1, v1, v1, v1 done compr vm
|
||||
; GCN-DAG: v_add_f32_e32 v0, 1.0, v1
|
||||
; GCN-DAG: s_add_i32 s0, s3, 2
|
||||
; GCN-DAG: s_mov_b32 s1, s2
|
||||
|
|
@ -231,7 +231,8 @@ define amdgpu_vs {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2
|
|||
|
||||
; GCN-LABEL: {{^}}structure_literal:
|
||||
; GCN: v_mov_b32_e32 v3, v0
|
||||
; GCN: exp 15, 0, -1, 1, -1, v3, v3, v3, v3
|
||||
; GCN: exp mrt0 v3, v3, v3, v3 done compr vm
|
||||
|
||||
; GCN-DAG: v_mov_b32_e32 v0, 1.0
|
||||
; GCN-DAG: s_mov_b32 s0, 2
|
||||
; GCN-DAG: s_mov_b32 s1, 3
|
||||
|
|
@ -242,3 +243,5 @@ define amdgpu_vs {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16
|
|||
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3)
|
||||
ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3, <2 x float> <float 2.0, float 4.0>}}
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "InitialPSInputAddr"="0" }
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 {
|
|||
; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7
|
||||
; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]]
|
||||
; CHECK-NEXT: ; BB#2:
|
||||
; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0
|
||||
; CHECK-NEXT: exp null off, off, off, off done vm
|
||||
; CHECK-NEXT: s_endpgm
|
||||
|
||||
; CHECK-NEXT: {{^}}[[SPLIT_BB]]:
|
||||
|
|
@ -158,7 +158,7 @@ exit:
|
|||
; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; CHECK-NEXT: ; BB#2:
|
||||
; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0
|
||||
; CHECK-NEXT: exp null off, off, off, off done vm
|
||||
; CHECK-NEXT: s_endpgm
|
||||
|
||||
; CHECK-NEXT: {{^}}[[SPLIT_BB]]:
|
||||
|
|
|
|||
Loading…
Reference in New Issue