forked from OSchip/llvm-project
AMDGPU/GlobalISel: Select llvm.amdgcn.div.scale
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@ -800,6 +800,40 @@ bool AMDGPUInstructionSelector::selectInterpP1F16(MachineInstr &MI) const {
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return true;
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}
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// We need to handle this here because tablegen doesn't support matching
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// instructions with multiple outputs.
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bool AMDGPUInstructionSelector::selectDivScale(MachineInstr &MI) const {
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Register Dst0 = MI.getOperand(0).getReg();
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Register Dst1 = MI.getOperand(1).getReg();
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LLT Ty = MRI->getType(Dst0);
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unsigned Opc;
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if (Ty == LLT::scalar(32))
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Opc = AMDGPU::V_DIV_SCALE_F32;
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else if (Ty == LLT::scalar(64))
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Opc = AMDGPU::V_DIV_SCALE_F64;
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else
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return false;
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const DebugLoc &DL = MI.getDebugLoc();
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MachineBasicBlock *MBB = MI.getParent();
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Register Numer = MI.getOperand(3).getReg();
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Register Denom = MI.getOperand(4).getReg();
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unsigned ChooseDenom = MI.getOperand(5).getImm();
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Register Src0 = ChooseDenom != 0 ? Numer : Denom;
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auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), Dst0)
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.addDef(Dst1)
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.addUse(Src0)
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.addUse(Denom)
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.addUse(Numer);
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MI.eraseFromParent();
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return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI);
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}
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bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
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unsigned IntrinsicID = I.getIntrinsicID();
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switch (IntrinsicID) {
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@ -832,6 +866,8 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I) const {
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return constrainCopyLikeIntrin(I, AMDGPU::SOFT_WQM);
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case Intrinsic::amdgcn_wwm:
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return constrainCopyLikeIntrin(I, AMDGPU::WWM);
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case Intrinsic::amdgcn_div_scale:
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return selectDivScale(I);
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default:
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return selectImpl(I, *CoverageInfo);
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}
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@ -104,6 +104,7 @@ private:
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bool selectG_INSERT(MachineInstr &I) const;
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bool selectInterpP1F16(MachineInstr &MI) const;
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bool selectDivScale(MachineInstr &MI) const;
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bool selectG_INTRINSIC(MachineInstr &I) const;
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bool selectEndCfIntrinsic(MachineInstr &MI) const;
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