forked from OSchip/llvm-project
[AArch64] Refactor floating point materialization. NFC
It splits the login of actual instruction emission away from the logic that figures out the appropriate sequence on AArch64ExpandPseudo::expandMOVImm. The new function AArch64_IMM::expandMOVImm, which return the list of the instructions to materialize the immediate constant, is implemented on a separated unit because it will be used in a subsequent patch to optimize floating point materialization. Reviewers: efriedma Differential Revision: https://reviews.llvm.org/D58915 llvm-svn: 356387
This commit is contained in:
Adhemerval Zanella
parent
0c962cb5c8
commit
8a595b1d2e
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//===- AArch64ExpandImm.h - AArch64 Immediate Expansion -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64ExpandImm stuff.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64ExpandImm.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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namespace llvm {
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namespace AArch64_IMM {
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/// Helper function which extracts the specified 16-bit chunk from a
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/// 64-bit value.
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static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
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assert(ChunkIdx < 4 && "Out of range chunk index specified!");
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return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
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}
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/// Check whether the given 16-bit chunk replicated to full 64-bit width
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/// can be materialized with an ORR instruction.
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static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
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Chunk = (Chunk << 48) | (Chunk << 32) | (Chunk << 16) | Chunk;
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return AArch64_AM::processLogicalImmediate(Chunk, 64, Encoding);
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}
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/// Check for identical 16-bit chunks within the constant and if so
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/// materialize them with a single ORR instruction. The remaining one or two
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/// 16-bit chunks will be materialized with MOVK instructions.
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///
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/// This allows us to materialize constants like |A|B|A|A| or |A|B|C|A| (order
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/// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
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/// an ORR instruction.
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static bool tryToreplicateChunks(uint64_t UImm,
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SmallVectorImpl<ImmInsnModel> &Insn) {
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using CountMap = DenseMap<uint64_t, unsigned>;
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CountMap Counts;
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// Scan the constant and count how often every chunk occurs.
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for (unsigned Idx = 0; Idx < 4; ++Idx)
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++Counts[getChunk(UImm, Idx)];
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// Traverse the chunks to find one which occurs more than once.
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for (CountMap::const_iterator Chunk = Counts.begin(), End = Counts.end();
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Chunk != End; ++Chunk) {
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const uint64_t ChunkVal = Chunk->first;
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const unsigned Count = Chunk->second;
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uint64_t Encoding = 0;
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// We are looking for chunks which have two or three instances and can be
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// materialized with an ORR instruction.
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if ((Count != 2 && Count != 3) || !canUseOrr(ChunkVal, Encoding))
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continue;
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const bool CountThree = Count == 3;
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Insn.push_back({ AArch64::ORRXri, 0, Encoding });
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unsigned ShiftAmt = 0;
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uint64_t Imm16 = 0;
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// Find the first chunk not materialized with the ORR instruction.
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for (; ShiftAmt < 64; ShiftAmt += 16) {
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Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
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if (Imm16 != ChunkVal)
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break;
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}
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// Create the first MOVK instruction.
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Insn.push_back({ AArch64::MOVKXi, Imm16,
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AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
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// In case we have three instances the whole constant is now materialized
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// and we can exit.
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if (CountThree)
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return true;
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// Find the remaining chunk which needs to be materialized.
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for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) {
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Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
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if (Imm16 != ChunkVal)
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break;
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}
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Insn.push_back({ AArch64::MOVKXi, Imm16,
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AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt) });
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return true;
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}
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return false;
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}
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/// Check whether this chunk matches the pattern '1...0...'. This pattern
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/// starts a contiguous sequence of ones if we look at the bits from the LSB
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/// towards the MSB.
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static bool isStartChunk(uint64_t Chunk) {
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if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
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return false;
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return isMask_64(~Chunk);
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}
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/// Check whether this chunk matches the pattern '0...1...' This pattern
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/// ends a contiguous sequence of ones if we look at the bits from the LSB
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/// towards the MSB.
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static bool isEndChunk(uint64_t Chunk) {
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if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
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return false;
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return isMask_64(Chunk);
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}
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/// Clear or set all bits in the chunk at the given index.
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static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
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const uint64_t Mask = 0xFFFF;
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if (Clear)
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// Clear chunk in the immediate.
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Imm &= ~(Mask << (Idx * 16));
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else
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// Set all bits in the immediate for the particular chunk.
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Imm |= Mask << (Idx * 16);
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return Imm;
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}
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/// Check whether the constant contains a sequence of contiguous ones,
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/// which might be interrupted by one or two chunks. If so, materialize the
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/// sequence of contiguous ones with an ORR instruction.
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/// Materialize the chunks which are either interrupting the sequence or outside
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/// of the sequence with a MOVK instruction.
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///
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/// Assuming S is a chunk which starts the sequence (1...0...), E is a chunk
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/// which ends the sequence (0...1...). Then we are looking for constants which
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/// contain at least one S and E chunk.
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/// E.g. |E|A|B|S|, |A|E|B|S| or |A|B|E|S|.
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///
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/// We are also looking for constants like |S|A|B|E| where the contiguous
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/// sequence of ones wraps around the MSB into the LSB.
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static bool trySequenceOfOnes(uint64_t UImm,
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SmallVectorImpl<ImmInsnModel> &Insn) {
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const int NotSet = -1;
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const uint64_t Mask = 0xFFFF;
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int StartIdx = NotSet;
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int EndIdx = NotSet;
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// Try to find the chunks which start/end a contiguous sequence of ones.
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for (int Idx = 0; Idx < 4; ++Idx) {
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int64_t Chunk = getChunk(UImm, Idx);
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// Sign extend the 16-bit chunk to 64-bit.
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Chunk = (Chunk << 48) >> 48;
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if (isStartChunk(Chunk))
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StartIdx = Idx;
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else if (isEndChunk(Chunk))
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EndIdx = Idx;
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}
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// Early exit in case we can't find a start/end chunk.
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if (StartIdx == NotSet || EndIdx == NotSet)
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return false;
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// Outside of the contiguous sequence of ones everything needs to be zero.
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uint64_t Outside = 0;
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// Chunks between the start and end chunk need to have all their bits set.
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uint64_t Inside = Mask;
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// If our contiguous sequence of ones wraps around from the MSB into the LSB,
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// just swap indices and pretend we are materializing a contiguous sequence
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// of zeros surrounded by a contiguous sequence of ones.
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if (StartIdx > EndIdx) {
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std::swap(StartIdx, EndIdx);
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std::swap(Outside, Inside);
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}
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uint64_t OrrImm = UImm;
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int FirstMovkIdx = NotSet;
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int SecondMovkIdx = NotSet;
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// Find out which chunks we need to patch up to obtain a contiguous sequence
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// of ones.
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for (int Idx = 0; Idx < 4; ++Idx) {
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const uint64_t Chunk = getChunk(UImm, Idx);
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// Check whether we are looking at a chunk which is not part of the
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// contiguous sequence of ones.
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if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) {
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OrrImm = updateImm(OrrImm, Idx, Outside == 0);
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// Remember the index we need to patch.
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if (FirstMovkIdx == NotSet)
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FirstMovkIdx = Idx;
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else
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SecondMovkIdx = Idx;
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// Check whether we are looking a chunk which is part of the contiguous
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// sequence of ones.
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} else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) {
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OrrImm = updateImm(OrrImm, Idx, Inside != Mask);
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// Remember the index we need to patch.
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if (FirstMovkIdx == NotSet)
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FirstMovkIdx = Idx;
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else
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SecondMovkIdx = Idx;
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}
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}
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assert(FirstMovkIdx != NotSet && "Constant materializable with single ORR!");
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// Create the ORR-immediate instruction.
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uint64_t Encoding = 0;
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AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
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Insn.push_back({ AArch64::ORRXri, 0, Encoding });
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const bool SingleMovk = SecondMovkIdx == NotSet;
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Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, FirstMovkIdx),
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AArch64_AM::getShifterImm(AArch64_AM::LSL,
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FirstMovkIdx * 16) });
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// Early exit in case we only need to emit a single MOVK instruction.
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if (SingleMovk)
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return true;
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// Create the second MOVK instruction.
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Insn.push_back({ AArch64::MOVKXi, getChunk(UImm, SecondMovkIdx),
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AArch64_AM::getShifterImm(AArch64_AM::LSL,
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SecondMovkIdx * 16) });
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return true;
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}
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/// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to a
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/// MOVZ or MOVN of width BitSize followed by up to 3 MOVK instructions.
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static inline void expandMOVImmSimple(uint64_t Imm, unsigned BitSize,
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unsigned OneChunks, unsigned ZeroChunks,
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SmallVectorImpl<ImmInsnModel> &Insn) {
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const unsigned Mask = 0xFFFF;
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// Use a MOVZ or MOVN instruction to set the high bits, followed by one or
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// more MOVK instructions to insert additional 16-bit portions into the
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// lower bits.
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bool isNeg = false;
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// Use MOVN to materialize the high bits if we have more all one chunks
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// than all zero chunks.
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if (OneChunks > ZeroChunks) {
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isNeg = true;
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Imm = ~Imm;
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}
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unsigned FirstOpc;
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if (BitSize == 32) {
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Imm &= (1LL << 32) - 1;
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FirstOpc = (isNeg ? AArch64::MOVNWi : AArch64::MOVZWi);
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} else {
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FirstOpc = (isNeg ? AArch64::MOVNXi : AArch64::MOVZXi);
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}
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unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
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unsigned LastShift = 0; // LSL amount for last MOVK
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if (Imm != 0) {
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unsigned LZ = countLeadingZeros(Imm);
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unsigned TZ = countTrailingZeros(Imm);
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Shift = (TZ / 16) * 16;
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LastShift = ((63 - LZ) / 16) * 16;
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}
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unsigned Imm16 = (Imm >> Shift) & Mask;
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Insn.push_back({ FirstOpc, Imm16,
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AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
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if (Shift == LastShift)
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return;
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// If a MOVN was used for the high bits of a negative value, flip the rest
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// of the bits back for use with MOVK.
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if (isNeg)
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Imm = ~Imm;
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unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
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while (Shift < LastShift) {
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Shift += 16;
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Imm16 = (Imm >> Shift) & Mask;
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if (Imm16 == (isNeg ? Mask : 0))
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continue; // This 16-bit portion is already set correctly.
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Insn.push_back({ Opc, Imm16,
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AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
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}
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}
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/// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
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/// real move-immediate instructions to synthesize the immediate.
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void expandMOVImm(uint64_t Imm, unsigned BitSize,
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SmallVectorImpl<ImmInsnModel> &Insn) {
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const unsigned Mask = 0xFFFF;
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// Scan the immediate and count the number of 16-bit chunks which are either
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// all ones or all zeros.
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unsigned OneChunks = 0;
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unsigned ZeroChunks = 0;
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for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
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const unsigned Chunk = (Imm >> Shift) & Mask;
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if (Chunk == Mask)
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OneChunks++;
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else if (Chunk == 0)
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ZeroChunks++;
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}
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// FIXME: Prefer MOVZ/MOVN over ORR because of the rules for the "mov"
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// alias.
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// Try a single ORR.
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uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
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uint64_t Encoding;
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if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
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unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
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Insn.push_back({ Opc, 0, Encoding });
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return;
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}
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// One to up three instruction sequences.
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//
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// Prefer MOVZ/MOVN followed by MOVK; it's more readable, and possibly the
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// fastest sequence with fast literal generation.
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if (OneChunks >= (BitSize / 16) - 2 || ZeroChunks >= (BitSize / 16) - 2) {
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expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
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return;
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}
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assert(BitSize == 64 && "All 32-bit immediates can be expanded with a"
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"MOVZ/MOVK pair");
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// Try other two-instruction sequences.
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// 64-bit ORR followed by MOVK.
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// We try to construct the ORR immediate in three different ways: either we
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// zero out the chunk which will be replaced, we fill the chunk which will
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// be replaced with ones, or we take the bit pattern from the other half of
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// the 64-bit immediate. This is comprehensive because of the way ORR
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// immediates are constructed.
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for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
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uint64_t ShiftedMask = (0xFFFFULL << Shift);
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uint64_t ZeroChunk = UImm & ~ShiftedMask;
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uint64_t OneChunk = UImm | ShiftedMask;
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uint64_t RotatedImm = (UImm << 32) | (UImm >> 32);
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uint64_t ReplicateChunk = ZeroChunk | (RotatedImm & ShiftedMask);
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if (AArch64_AM::processLogicalImmediate(ZeroChunk, BitSize, Encoding) ||
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AArch64_AM::processLogicalImmediate(OneChunk, BitSize, Encoding) ||
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AArch64_AM::processLogicalImmediate(ReplicateChunk, BitSize,
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Encoding)) {
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// Create the ORR-immediate instruction.
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Insn.push_back({ AArch64::ORRXri, 0, Encoding });
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// Create the MOVK instruction.
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const unsigned Imm16 = getChunk(UImm, Shift / 16);
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Insn.push_back({ AArch64::MOVKXi, Imm16,
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AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift) });
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return;
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}
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}
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// FIXME: Add more two-instruction sequences.
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// Three instruction sequences.
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//
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// Prefer MOVZ/MOVN followed by two MOVK; it's more readable, and possibly
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// the fastest sequence with fast literal generation. (If neither MOVK is
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// part of a fast literal generation pair, it could be slower than the
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// four-instruction sequence, but we won't worry about that for now.)
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if (OneChunks || ZeroChunks) {
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expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
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return;
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}
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// Check for identical 16-bit chunks within the constant and if so materialize
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// them with a single ORR instruction. The remaining one or two 16-bit chunks
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// will be materialized with MOVK instructions.
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if (BitSize == 64 && tryToreplicateChunks(UImm, Insn))
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return;
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// Check whether the constant contains a sequence of contiguous ones, which
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// might be interrupted by one or two chunks. If so, materialize the sequence
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// of contiguous ones with an ORR instruction. Materialize the chunks which
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// are either interrupting the sequence or outside of the sequence with a
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// MOVK instruction.
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if (BitSize == 64 && trySequenceOfOnes(UImm, Insn))
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return;
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// We found no possible two or three instruction sequence; use the general
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// four-instruction sequence.
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expandMOVImmSimple(Imm, BitSize, OneChunks, ZeroChunks, Insn);
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}
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} // end namespace AArch64_AM
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} // end namespace llvm
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@ -0,0 +1,35 @@
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//===- AArch64ExpandImm.h - AArch64 Immediate Expansion ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 immediate expansion stuff.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64EXPANDIMM_H
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#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64EXPANDIMM_H
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#include "llvm/ADT/SmallVector.h"
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namespace llvm {
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namespace AArch64_IMM {
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struct ImmInsnModel {
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unsigned Opcode;
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uint64_t Op1;
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uint64_t Op2;
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};
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void expandMOVImm(uint64_t Imm, unsigned BitSize,
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SmallVectorImpl<ImmInsnModel> &Insn);
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} // end namespace AArch64_IMM
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||||
} // end namespace llvm
|
||||
|
||||
#endif
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "AArch64ExpandImm.h"
|
||||
#include "AArch64InstrInfo.h"
|
||||
#include "AArch64Subtarget.h"
|
||||
#include "MCTargetDesc/AArch64AddressingModes.h"
|
||||
|
|
@ -65,11 +66,6 @@ private:
|
|||
MachineBasicBlock::iterator &NextMBBI);
|
||||
bool expandMOVImm(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
unsigned BitSize);
|
||||
bool expandMOVImmSimple(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned BitSize,
|
||||
unsigned OneChunks,
|
||||
unsigned ZeroChunks);
|
||||
|
||||
bool expandCMP_SWAP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
unsigned LdarOp, unsigned StlrOp, unsigned CmpOp,
|
||||
|
|
@ -103,279 +99,6 @@ static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
|
|||
}
|
||||
}
|
||||
|
||||
/// Helper function which extracts the specified 16-bit chunk from a
|
||||
/// 64-bit value.
|
||||
static uint64_t getChunk(uint64_t Imm, unsigned ChunkIdx) {
|
||||
assert(ChunkIdx < 4 && "Out of range chunk index specified!");
|
||||
|
||||
return (Imm >> (ChunkIdx * 16)) & 0xFFFF;
|
||||
}
|
||||
|
||||
/// Check whether the given 16-bit chunk replicated to full 64-bit width
|
||||
/// can be materialized with an ORR instruction.
|
||||
static bool canUseOrr(uint64_t Chunk, uint64_t &Encoding) {
|
||||
Chunk = (Chunk << 48) | (Chunk << 32) | (Chunk << 16) | Chunk;
|
||||
|
||||
return AArch64_AM::processLogicalImmediate(Chunk, 64, Encoding);
|
||||
}
|
||||
|
||||
/// Check for identical 16-bit chunks within the constant and if so
|
||||
/// materialize them with a single ORR instruction. The remaining one or two
|
||||
/// 16-bit chunks will be materialized with MOVK instructions.
|
||||
///
|
||||
/// This allows us to materialize constants like |A|B|A|A| or |A|B|C|A| (order
|
||||
/// of the chunks doesn't matter), assuming |A|A|A|A| can be materialized with
|
||||
/// an ORR instruction.
|
||||
static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator &MBBI,
|
||||
const AArch64InstrInfo *TII) {
|
||||
using CountMap = DenseMap<uint64_t, unsigned>;
|
||||
|
||||
CountMap Counts;
|
||||
|
||||
// Scan the constant and count how often every chunk occurs.
|
||||
for (unsigned Idx = 0; Idx < 4; ++Idx)
|
||||
++Counts[getChunk(UImm, Idx)];
|
||||
|
||||
// Traverse the chunks to find one which occurs more than once.
|
||||
for (CountMap::const_iterator Chunk = Counts.begin(), End = Counts.end();
|
||||
Chunk != End; ++Chunk) {
|
||||
const uint64_t ChunkVal = Chunk->first;
|
||||
const unsigned Count = Chunk->second;
|
||||
|
||||
uint64_t Encoding = 0;
|
||||
|
||||
// We are looking for chunks which have two or three instances and can be
|
||||
// materialized with an ORR instruction.
|
||||
if ((Count != 2 && Count != 3) || !canUseOrr(ChunkVal, Encoding))
|
||||
continue;
|
||||
|
||||
const bool CountThree = Count == 3;
|
||||
// Create the ORR-immediate instruction.
|
||||
MachineInstrBuilder MIB =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
|
||||
.add(MI.getOperand(0))
|
||||
.addReg(AArch64::XZR)
|
||||
.addImm(Encoding);
|
||||
|
||||
const unsigned DstReg = MI.getOperand(0).getReg();
|
||||
const bool DstIsDead = MI.getOperand(0).isDead();
|
||||
|
||||
unsigned ShiftAmt = 0;
|
||||
uint64_t Imm16 = 0;
|
||||
// Find the first chunk not materialized with the ORR instruction.
|
||||
for (; ShiftAmt < 64; ShiftAmt += 16) {
|
||||
Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
|
||||
|
||||
if (Imm16 != ChunkVal)
|
||||
break;
|
||||
}
|
||||
|
||||
// Create the first MOVK instruction.
|
||||
MachineInstrBuilder MIB1 =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
|
||||
.addReg(DstReg,
|
||||
RegState::Define | getDeadRegState(DstIsDead && CountThree))
|
||||
.addReg(DstReg)
|
||||
.addImm(Imm16)
|
||||
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
|
||||
|
||||
// In case we have three instances the whole constant is now materialized
|
||||
// and we can exit.
|
||||
if (CountThree) {
|
||||
transferImpOps(MI, MIB, MIB1);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
// Find the remaining chunk which needs to be materialized.
|
||||
for (ShiftAmt += 16; ShiftAmt < 64; ShiftAmt += 16) {
|
||||
Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
|
||||
|
||||
if (Imm16 != ChunkVal)
|
||||
break;
|
||||
}
|
||||
|
||||
// Create the second MOVK instruction.
|
||||
MachineInstrBuilder MIB2 =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
|
||||
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
|
||||
.addReg(DstReg)
|
||||
.addImm(Imm16)
|
||||
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
|
||||
|
||||
transferImpOps(MI, MIB, MIB2);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/// Check whether this chunk matches the pattern '1...0...'. This pattern
|
||||
/// starts a contiguous sequence of ones if we look at the bits from the LSB
|
||||
/// towards the MSB.
|
||||
static bool isStartChunk(uint64_t Chunk) {
|
||||
if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
|
||||
return false;
|
||||
|
||||
return isMask_64(~Chunk);
|
||||
}
|
||||
|
||||
/// Check whether this chunk matches the pattern '0...1...' This pattern
|
||||
/// ends a contiguous sequence of ones if we look at the bits from the LSB
|
||||
/// towards the MSB.
|
||||
static bool isEndChunk(uint64_t Chunk) {
|
||||
if (Chunk == 0 || Chunk == std::numeric_limits<uint64_t>::max())
|
||||
return false;
|
||||
|
||||
return isMask_64(Chunk);
|
||||
}
|
||||
|
||||
/// Clear or set all bits in the chunk at the given index.
|
||||
static uint64_t updateImm(uint64_t Imm, unsigned Idx, bool Clear) {
|
||||
const uint64_t Mask = 0xFFFF;
|
||||
|
||||
if (Clear)
|
||||
// Clear chunk in the immediate.
|
||||
Imm &= ~(Mask << (Idx * 16));
|
||||
else
|
||||
// Set all bits in the immediate for the particular chunk.
|
||||
Imm |= Mask << (Idx * 16);
|
||||
|
||||
return Imm;
|
||||
}
|
||||
|
||||
/// Check whether the constant contains a sequence of contiguous ones,
|
||||
/// which might be interrupted by one or two chunks. If so, materialize the
|
||||
/// sequence of contiguous ones with an ORR instruction.
|
||||
/// Materialize the chunks which are either interrupting the sequence or outside
|
||||
/// of the sequence with a MOVK instruction.
|
||||
///
|
||||
/// Assuming S is a chunk which starts the sequence (1...0...), E is a chunk
|
||||
/// which ends the sequence (0...1...). Then we are looking for constants which
|
||||
/// contain at least one S and E chunk.
|
||||
/// E.g. |E|A|B|S|, |A|E|B|S| or |A|B|E|S|.
|
||||
///
|
||||
/// We are also looking for constants like |S|A|B|E| where the contiguous
|
||||
/// sequence of ones wraps around the MSB into the LSB.
|
||||
static bool trySequenceOfOnes(uint64_t UImm, MachineInstr &MI,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator &MBBI,
|
||||
const AArch64InstrInfo *TII) {
|
||||
const int NotSet = -1;
|
||||
const uint64_t Mask = 0xFFFF;
|
||||
|
||||
int StartIdx = NotSet;
|
||||
int EndIdx = NotSet;
|
||||
// Try to find the chunks which start/end a contiguous sequence of ones.
|
||||
for (int Idx = 0; Idx < 4; ++Idx) {
|
||||
int64_t Chunk = getChunk(UImm, Idx);
|
||||
// Sign extend the 16-bit chunk to 64-bit.
|
||||
Chunk = (Chunk << 48) >> 48;
|
||||
|
||||
if (isStartChunk(Chunk))
|
||||
StartIdx = Idx;
|
||||
else if (isEndChunk(Chunk))
|
||||
EndIdx = Idx;
|
||||
}
|
||||
|
||||
// Early exit in case we can't find a start/end chunk.
|
||||
if (StartIdx == NotSet || EndIdx == NotSet)
|
||||
return false;
|
||||
|
||||
// Outside of the contiguous sequence of ones everything needs to be zero.
|
||||
uint64_t Outside = 0;
|
||||
// Chunks between the start and end chunk need to have all their bits set.
|
||||
uint64_t Inside = Mask;
|
||||
|
||||
// If our contiguous sequence of ones wraps around from the MSB into the LSB,
|
||||
// just swap indices and pretend we are materializing a contiguous sequence
|
||||
// of zeros surrounded by a contiguous sequence of ones.
|
||||
if (StartIdx > EndIdx) {
|
||||
std::swap(StartIdx, EndIdx);
|
||||
std::swap(Outside, Inside);
|
||||
}
|
||||
|
||||
uint64_t OrrImm = UImm;
|
||||
int FirstMovkIdx = NotSet;
|
||||
int SecondMovkIdx = NotSet;
|
||||
|
||||
// Find out which chunks we need to patch up to obtain a contiguous sequence
|
||||
// of ones.
|
||||
for (int Idx = 0; Idx < 4; ++Idx) {
|
||||
const uint64_t Chunk = getChunk(UImm, Idx);
|
||||
|
||||
// Check whether we are looking at a chunk which is not part of the
|
||||
// contiguous sequence of ones.
|
||||
if ((Idx < StartIdx || EndIdx < Idx) && Chunk != Outside) {
|
||||
OrrImm = updateImm(OrrImm, Idx, Outside == 0);
|
||||
|
||||
// Remember the index we need to patch.
|
||||
if (FirstMovkIdx == NotSet)
|
||||
FirstMovkIdx = Idx;
|
||||
else
|
||||
SecondMovkIdx = Idx;
|
||||
|
||||
// Check whether we are looking a chunk which is part of the contiguous
|
||||
// sequence of ones.
|
||||
} else if (Idx > StartIdx && Idx < EndIdx && Chunk != Inside) {
|
||||
OrrImm = updateImm(OrrImm, Idx, Inside != Mask);
|
||||
|
||||
// Remember the index we need to patch.
|
||||
if (FirstMovkIdx == NotSet)
|
||||
FirstMovkIdx = Idx;
|
||||
else
|
||||
SecondMovkIdx = Idx;
|
||||
}
|
||||
}
|
||||
assert(FirstMovkIdx != NotSet && "Constant materializable with single ORR!");
|
||||
|
||||
// Create the ORR-immediate instruction.
|
||||
uint64_t Encoding = 0;
|
||||
AArch64_AM::processLogicalImmediate(OrrImm, 64, Encoding);
|
||||
MachineInstrBuilder MIB =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
|
||||
.add(MI.getOperand(0))
|
||||
.addReg(AArch64::XZR)
|
||||
.addImm(Encoding);
|
||||
|
||||
const unsigned DstReg = MI.getOperand(0).getReg();
|
||||
const bool DstIsDead = MI.getOperand(0).isDead();
|
||||
|
||||
const bool SingleMovk = SecondMovkIdx == NotSet;
|
||||
// Create the first MOVK instruction.
|
||||
MachineInstrBuilder MIB1 =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
|
||||
.addReg(DstReg,
|
||||
RegState::Define | getDeadRegState(DstIsDead && SingleMovk))
|
||||
.addReg(DstReg)
|
||||
.addImm(getChunk(UImm, FirstMovkIdx))
|
||||
.addImm(
|
||||
AArch64_AM::getShifterImm(AArch64_AM::LSL, FirstMovkIdx * 16));
|
||||
|
||||
// Early exit in case we only need to emit a single MOVK instruction.
|
||||
if (SingleMovk) {
|
||||
transferImpOps(MI, MIB, MIB1);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
// Create the second MOVK instruction.
|
||||
MachineInstrBuilder MIB2 =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
|
||||
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
|
||||
.addReg(DstReg)
|
||||
.addImm(getChunk(UImm, SecondMovkIdx))
|
||||
.addImm(
|
||||
AArch64_AM::getShifterImm(AArch64_AM::LSL, SecondMovkIdx * 16));
|
||||
|
||||
transferImpOps(MI, MIB, MIB2);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
/// Expand a MOVi32imm or MOVi64imm pseudo instruction to one or more
|
||||
/// real move-immediate instructions to synthesize the immediate.
|
||||
bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
|
||||
|
|
@ -384,7 +107,6 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
|
|||
MachineInstr &MI = *MBBI;
|
||||
unsigned DstReg = MI.getOperand(0).getReg();
|
||||
uint64_t Imm = MI.getOperand(1).getImm();
|
||||
const unsigned Mask = 0xFFFF;
|
||||
|
||||
if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) {
|
||||
// Useless def, and we don't want to risk creating an invalid ORR (which
|
||||
|
|
@ -393,194 +115,50 @@ bool AArch64ExpandPseudo::expandMOVImm(MachineBasicBlock &MBB,
|
|||
return true;
|
||||
}
|
||||
|
||||
// Scan the immediate and count the number of 16-bit chunks which are either
|
||||
// all ones or all zeros.
|
||||
unsigned OneChunks = 0;
|
||||
unsigned ZeroChunks = 0;
|
||||
for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
|
||||
const unsigned Chunk = (Imm >> Shift) & Mask;
|
||||
if (Chunk == Mask)
|
||||
OneChunks++;
|
||||
else if (Chunk == 0)
|
||||
ZeroChunks++;
|
||||
}
|
||||
SmallVector<AArch64_IMM::ImmInsnModel, 4> Insn;
|
||||
AArch64_IMM::expandMOVImm(Imm, BitSize, Insn);
|
||||
assert(Insn.size() != 0);
|
||||
|
||||
// FIXME: Prefer MOVZ/MOVN over ORR because of the rules for the "mov"
|
||||
// alias.
|
||||
SmallVector<MachineInstrBuilder, 4> MIBS;
|
||||
for (auto I = Insn.begin(), E = Insn.end(); I != E; ++I) {
|
||||
bool LastItem = std::next(I) == E;
|
||||
switch (I->Opcode)
|
||||
{
|
||||
default: llvm_unreachable("unhandled!"); break;
|
||||
|
||||
// Try a single ORR.
|
||||
uint64_t UImm = Imm << (64 - BitSize) >> (64 - BitSize);
|
||||
uint64_t Encoding;
|
||||
if (AArch64_AM::processLogicalImmediate(UImm, BitSize, Encoding)) {
|
||||
unsigned Opc = (BitSize == 32 ? AArch64::ORRWri : AArch64::ORRXri);
|
||||
MachineInstrBuilder MIB =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
|
||||
.add(MI.getOperand(0))
|
||||
.addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
|
||||
.addImm(Encoding);
|
||||
transferImpOps(MI, MIB, MIB);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
// Two instruction sequences.
|
||||
//
|
||||
// Prefer MOVZ/MOVN followed by MOVK; it's more readable, and possibly the
|
||||
// fastest sequence with fast literal generation.
|
||||
if (OneChunks >= (BitSize / 16) - 2 || ZeroChunks >= (BitSize / 16) - 2)
|
||||
return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
|
||||
|
||||
assert(BitSize == 64 && "All 32-bit immediates can be expanded with a"
|
||||
"MOVZ/MOVK pair");
|
||||
|
||||
// Try other two-instruction sequences.
|
||||
|
||||
// 64-bit ORR followed by MOVK.
|
||||
// We try to construct the ORR immediate in three different ways: either we
|
||||
// zero out the chunk which will be replaced, we fill the chunk which will
|
||||
// be replaced with ones, or we take the bit pattern from the other half of
|
||||
// the 64-bit immediate. This is comprehensive because of the way ORR
|
||||
// immediates are constructed.
|
||||
for (unsigned Shift = 0; Shift < BitSize; Shift += 16) {
|
||||
uint64_t ShiftedMask = (0xFFFFULL << Shift);
|
||||
uint64_t ZeroChunk = UImm & ~ShiftedMask;
|
||||
uint64_t OneChunk = UImm | ShiftedMask;
|
||||
uint64_t RotatedImm = (UImm << 32) | (UImm >> 32);
|
||||
uint64_t ReplicateChunk = ZeroChunk | (RotatedImm & ShiftedMask);
|
||||
if (AArch64_AM::processLogicalImmediate(ZeroChunk, BitSize, Encoding) ||
|
||||
AArch64_AM::processLogicalImmediate(OneChunk, BitSize, Encoding) ||
|
||||
AArch64_AM::processLogicalImmediate(ReplicateChunk,
|
||||
BitSize, Encoding)) {
|
||||
// Create the ORR-immediate instruction.
|
||||
MachineInstrBuilder MIB =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
|
||||
.add(MI.getOperand(0))
|
||||
.addReg(AArch64::XZR)
|
||||
.addImm(Encoding);
|
||||
|
||||
// Create the MOVK instruction.
|
||||
const unsigned Imm16 = getChunk(UImm, Shift / 16);
|
||||
const unsigned DstReg = MI.getOperand(0).getReg();
|
||||
const bool DstIsDead = MI.getOperand(0).isDead();
|
||||
MachineInstrBuilder MIB1 =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
|
||||
.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
|
||||
.addReg(DstReg)
|
||||
.addImm(Imm16)
|
||||
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
|
||||
|
||||
transferImpOps(MI, MIB, MIB1);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
case AArch64::ORRWri:
|
||||
case AArch64::ORRXri:
|
||||
MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
|
||||
.add(MI.getOperand(0))
|
||||
.addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
|
||||
.addImm(I->Op2));
|
||||
break;
|
||||
case AArch64::MOVNWi:
|
||||
case AArch64::MOVNXi:
|
||||
case AArch64::MOVZWi:
|
||||
case AArch64::MOVZXi: {
|
||||
bool DstIsDead = MI.getOperand(0).isDead();
|
||||
MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
|
||||
.addReg(DstReg, RegState::Define |
|
||||
getDeadRegState(DstIsDead && LastItem))
|
||||
.addImm(I->Op1)
|
||||
.addImm(I->Op2));
|
||||
} break;
|
||||
case AArch64::MOVKWi:
|
||||
case AArch64::MOVKXi: {
|
||||
unsigned DstReg = MI.getOperand(0).getReg();
|
||||
bool DstIsDead = MI.getOperand(0).isDead();
|
||||
MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode))
|
||||
.addReg(DstReg,
|
||||
RegState::Define |
|
||||
getDeadRegState(DstIsDead && LastItem))
|
||||
.addReg(DstReg)
|
||||
.addImm(I->Op1)
|
||||
.addImm(I->Op2));
|
||||
} break;
|
||||
}
|
||||
}
|
||||
|
||||
// FIXME: Add more two-instruction sequences.
|
||||
|
||||
// Three instruction sequences.
|
||||
//
|
||||
// Prefer MOVZ/MOVN followed by two MOVK; it's more readable, and possibly
|
||||
// the fastest sequence with fast literal generation. (If neither MOVK is
|
||||
// part of a fast literal generation pair, it could be slower than the
|
||||
// four-instruction sequence, but we won't worry about that for now.)
|
||||
if (OneChunks || ZeroChunks)
|
||||
return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
|
||||
|
||||
// Check for identical 16-bit chunks within the constant and if so materialize
|
||||
// them with a single ORR instruction. The remaining one or two 16-bit chunks
|
||||
// will be materialized with MOVK instructions.
|
||||
if (BitSize == 64 && tryToreplicateChunks(UImm, MI, MBB, MBBI, TII))
|
||||
return true;
|
||||
|
||||
// Check whether the constant contains a sequence of contiguous ones, which
|
||||
// might be interrupted by one or two chunks. If so, materialize the sequence
|
||||
// of contiguous ones with an ORR instruction. Materialize the chunks which
|
||||
// are either interrupting the sequence or outside of the sequence with a
|
||||
// MOVK instruction.
|
||||
if (BitSize == 64 && trySequenceOfOnes(UImm, MI, MBB, MBBI, TII))
|
||||
return true;
|
||||
|
||||
// We found no possible two or three instruction sequence; use the general
|
||||
// four-instruction sequence.
|
||||
return expandMOVImmSimple(MBB, MBBI, BitSize, OneChunks, ZeroChunks);
|
||||
}
|
||||
|
||||
/// \brief Expand a MOVi32imm or MOVi64imm pseudo instruction to a
|
||||
/// MOVZ or MOVN of width BitSize followed by up to 3 MOVK instructions.
|
||||
bool AArch64ExpandPseudo::expandMOVImmSimple(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned BitSize,
|
||||
unsigned OneChunks,
|
||||
unsigned ZeroChunks) {
|
||||
MachineInstr &MI = *MBBI;
|
||||
unsigned DstReg = MI.getOperand(0).getReg();
|
||||
uint64_t Imm = MI.getOperand(1).getImm();
|
||||
const unsigned Mask = 0xFFFF;
|
||||
|
||||
// Use a MOVZ or MOVN instruction to set the high bits, followed by one or
|
||||
// more MOVK instructions to insert additional 16-bit portions into the
|
||||
// lower bits.
|
||||
bool isNeg = false;
|
||||
|
||||
// Use MOVN to materialize the high bits if we have more all one chunks
|
||||
// than all zero chunks.
|
||||
if (OneChunks > ZeroChunks) {
|
||||
isNeg = true;
|
||||
Imm = ~Imm;
|
||||
}
|
||||
|
||||
unsigned FirstOpc;
|
||||
if (BitSize == 32) {
|
||||
Imm &= (1LL << 32) - 1;
|
||||
FirstOpc = (isNeg ? AArch64::MOVNWi : AArch64::MOVZWi);
|
||||
} else {
|
||||
FirstOpc = (isNeg ? AArch64::MOVNXi : AArch64::MOVZXi);
|
||||
}
|
||||
unsigned Shift = 0; // LSL amount for high bits with MOVZ/MOVN
|
||||
unsigned LastShift = 0; // LSL amount for last MOVK
|
||||
if (Imm != 0) {
|
||||
unsigned LZ = countLeadingZeros(Imm);
|
||||
unsigned TZ = countTrailingZeros(Imm);
|
||||
Shift = (TZ / 16) * 16;
|
||||
LastShift = ((63 - LZ) / 16) * 16;
|
||||
}
|
||||
unsigned Imm16 = (Imm >> Shift) & Mask;
|
||||
bool DstIsDead = MI.getOperand(0).isDead();
|
||||
MachineInstrBuilder MIB1 =
|
||||
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(FirstOpc))
|
||||
.addReg(DstReg, RegState::Define |
|
||||
getDeadRegState(DstIsDead && Shift == LastShift))
|
||||
.addImm(Imm16)
|
||||
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
|
||||
|
||||
// If a MOVN was used for the high bits of a negative value, flip the rest
|
||||
// of the bits back for use with MOVK.
|
||||
if (isNeg)
|
||||
Imm = ~Imm;
|
||||
|
||||
if (Shift == LastShift) {
|
||||
transferImpOps(MI, MIB1, MIB1);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
||||
MachineInstrBuilder MIB2;
|
||||
unsigned Opc = (BitSize == 32 ? AArch64::MOVKWi : AArch64::MOVKXi);
|
||||
while (Shift < LastShift) {
|
||||
Shift += 16;
|
||||
Imm16 = (Imm >> Shift) & Mask;
|
||||
if (Imm16 == (isNeg ? Mask : 0))
|
||||
continue; // This 16-bit portion is already set correctly.
|
||||
MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc))
|
||||
.addReg(DstReg,
|
||||
RegState::Define |
|
||||
getDeadRegState(DstIsDead && Shift == LastShift))
|
||||
.addReg(DstReg)
|
||||
.addImm(Imm16)
|
||||
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, Shift));
|
||||
}
|
||||
|
||||
transferImpOps(MI, MIB1, MIB2);
|
||||
transferImpOps(MI, MIBS.front(), MIBS.back());
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,6 +31,7 @@ add_llvm_target(AArch64CodeGen
|
|||
AArch64CondBrTuning.cpp
|
||||
AArch64ConditionalCompares.cpp
|
||||
AArch64DeadRegisterDefinitionsPass.cpp
|
||||
AArch64ExpandImm.cpp
|
||||
AArch64ExpandPseudoInsts.cpp
|
||||
AArch64FalkorHWPFFix.cpp
|
||||
AArch64FastISel.cpp
|
||||
|
|
|
|||
Loading…
Reference in New Issue