forked from OSchip/llvm-project
Revert "Revert r362867: [ELF][PPC] Simplify {read,write}FromHalf16"
This reverts commit r363060 and restores r362867.
r362867 is innocent. The ppc64le-lld-multistage-test bot failure was due to a clang/gcc .toc bug:
ld.lld: error: relocation refers to a discarded section: .rodata._ZNK4llvm3MVT13getSizeInBitsEv
>>> defined in utils/TableGen/CMakeFiles/llvm-tblgen.dir/CodeGenRegisters.cpp.o
>>> referenced by CodeGenRegisters.cpp
>>> utils/TableGen/CMakeFiles/llvm-tblgen.dir/CodeGenRegisters.cpp.o:(.toc+0x0)
It will be worked around by D63182.
llvm-svn: 363124
This commit is contained in:
Fangrui Song
parent
aa6f2af4e6
commit
8a529f3cea
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@ -53,11 +53,11 @@ static uint16_t lo(uint32_t V) { return V; }
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static uint16_t ha(uint32_t V) { return (V + 0x8000) >> 16; }
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static uint32_t readFromHalf16(const uint8_t *Loc) {
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return read32(Loc - (Config->EKind == ELF32BEKind ? 2 : 0));
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return read32(Config->IsLE ? Loc : Loc - 2);
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}
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static void writeFromHalf16(uint8_t *Loc, uint32_t Insn) {
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write32(Loc - (Config->EKind == ELF32BEKind ? 2 : 0), Insn);
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write32(Config->IsLE ? Loc : Loc - 2, Insn);
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}
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void elf::writePPC32GlinkSection(uint8_t *Buf, size_t NumEntries) {
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@ -274,12 +274,12 @@ static bool isInstructionUpdateForm(uint32_t Encoding) {
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// pointer is pointing into the middle of the word we want to extract, and on
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// little-endian it is pointing to the start of the word. These 2 helpers are to
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// simplify reading and writing in that context.
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static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) {
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write32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0), Instr);
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static void writeFromHalf16(uint8_t *Loc, uint32_t Insn) {
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write32(Config->IsLE ? Loc : Loc - 2, Insn);
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}
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static uint32_t readInstrFromHalf16(const uint8_t *Loc) {
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return read32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0));
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static uint32_t readFromHalf16(const uint8_t *Loc) {
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return read32(Config->IsLE ? Loc : Loc - 2);
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}
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PPC64::PPC64() {
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@ -362,10 +362,10 @@ void PPC64::relaxGot(uint8_t *Loc, RelType Type, uint64_t Val) const {
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case R_PPC64_TOC16_LO_DS: {
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// Convert "ld reg, .LC0@toc@l(reg)" to "addi reg, reg, var@toc@l" or
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// "addi reg, 2, var@toc".
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uint32_t Instr = readInstrFromHalf16(Loc);
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if (getPrimaryOpCode(Instr) != LD)
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uint32_t Insn = readFromHalf16(Loc);
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if (getPrimaryOpCode(Insn) != LD)
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error("expected a 'ld' for got-indirect to toc-relative relaxing");
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writeInstrFromHalf16(Loc, (Instr & 0x03FFFFFF) | 0x38000000);
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writeFromHalf16(Loc, (Insn & 0x03ffffff) | 0x38000000);
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relocateOne(Loc, R_PPC64_TOC16_LO, Val);
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break;
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}
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@ -392,11 +392,11 @@ void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
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switch (Type) {
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case R_PPC64_GOT_TLSGD16_HA:
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writeInstrFromHalf16(Loc, 0x60000000); // nop
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writeFromHalf16(Loc, 0x60000000); // nop
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break;
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case R_PPC64_GOT_TLSGD16:
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case R_PPC64_GOT_TLSGD16_LO:
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writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13
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writeFromHalf16(Loc, 0x3c6d0000); // addis r3, r13
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relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
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break;
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case R_PPC64_TLSGD:
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@ -431,10 +431,10 @@ void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
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switch (Type) {
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case R_PPC64_GOT_TLSLD16_HA:
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writeInstrFromHalf16(Loc, 0x60000000); // nop
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writeFromHalf16(Loc, 0x60000000); // nop
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break;
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case R_PPC64_GOT_TLSLD16_LO:
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writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0
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writeFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0
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break;
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case R_PPC64_TLSLD:
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write32(Loc, 0x60000000); // nop
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@ -758,7 +758,7 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
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checkInt(Loc, Val, 16, OriginalType);
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// DQ-form instructions use bits 28-31 as part of the instruction encoding
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// DS-form instructions only use bits 30-31.
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uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 0xF : 0x3;
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uint16_t Mask = isDQFormInstruction(readFromHalf16(Loc)) ? 0xf : 0x3;
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checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
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write16(Loc, (read16(Loc) & Mask) | lo(Val));
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} break;
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@ -766,7 +766,7 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
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case R_PPC64_REL16_HA:
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case R_PPC64_TPREL16_HA:
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if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0)
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writeInstrFromHalf16(Loc, 0x60000000);
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writeFromHalf16(Loc, 0x60000000);
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else
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write16(Loc, ha(Val));
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break;
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@ -798,35 +798,36 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
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// changed into a nop. The lo part then needs to be updated to use the
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// toc-pointer register r2, as the base register.
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if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
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uint32_t Instr = readInstrFromHalf16(Loc);
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if (isInstructionUpdateForm(Instr))
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uint32_t Insn = readFromHalf16(Loc);
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if (isInstructionUpdateForm(Insn))
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error(getErrorLocation(Loc) +
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"can't toc-optimize an update instruction: 0x" +
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utohexstr(Instr));
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Instr = (Instr & 0xFFE00000) | 0x00020000;
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writeInstrFromHalf16(Loc, Instr);
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utohexstr(Insn));
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writeFromHalf16(Loc, (Insn & 0xffe00000) | 0x00020000 | lo(Val));
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} else {
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write16(Loc, lo(Val));
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}
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write16(Loc, lo(Val));
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break;
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case R_PPC64_ADDR16_LO_DS:
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case R_PPC64_TPREL16_LO_DS: {
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// DQ-form instructions use bits 28-31 as part of the instruction encoding
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// DS-form instructions only use bits 30-31.
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uint32_t Inst = readInstrFromHalf16(Loc);
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uint16_t Mask = isDQFormInstruction(Inst) ? 0xF : 0x3;
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uint32_t Insn = readFromHalf16(Loc);
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uint16_t Mask = isDQFormInstruction(Insn) ? 0xf : 0x3;
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checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
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if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
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// When the high-adjusted part of a toc relocation evalutes to 0, it is
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// changed into a nop. The lo part then needs to be updated to use the toc
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// pointer register r2, as the base register.
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if (isInstructionUpdateForm(Inst))
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if (isInstructionUpdateForm(Insn))
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error(getErrorLocation(Loc) +
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"Can't toc-optimize an update instruction: 0x" +
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Twine::utohexstr(Inst));
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Inst = (Inst & 0xFFE0000F) | 0x00020000;
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writeInstrFromHalf16(Loc, Inst);
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Twine::utohexstr(Insn));
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Insn &= 0xffe00000 | Mask;
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writeFromHalf16(Loc, Insn | 0x00020000 | lo(Val));
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} else {
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write16(Loc, (read16(Loc) & Mask) | lo(Val));
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}
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write16(Loc, (read16(Loc) & Mask) | lo(Val));
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} break;
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case R_PPC64_ADDR32:
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case R_PPC64_REL32:
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@ -935,8 +936,8 @@ void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
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case R_PPC64_GOT_TLSGD16_LO: {
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// Relax from addi r3, rA, sym@got@tlsgd@l to
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// ld r3, sym@got@tprel@l(rA)
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uint32_t InputRegister = (readInstrFromHalf16(Loc) & (0x1f << 16));
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writeInstrFromHalf16(Loc, 0xE8600000 | InputRegister);
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uint32_t RA = (readFromHalf16(Loc) & (0x1f << 16));
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writeFromHalf16(Loc, 0xe8600000 | RA);
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relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val);
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return;
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}
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