forked from OSchip/llvm-project
Fix PR1325: Case range optimization was performed in the case it
shouldn't. Also fix some "latent" bug on 64-bit platforms llvm-svn: 35990
This commit is contained in:
Anton Korobeynikov
parent
b4a7326c20
commit
8a1a84f96e
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@ -1678,8 +1678,6 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
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CaseRecVector& WorkList,
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Value* SV,
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MachineBasicBlock* Default){
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return false; // DISABLED FOR NOW: PR1325.
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unsigned IntPtrBits = getSizeInBits(TLI.getPointerTy());
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Case& FrontCase = *CR.Range.first;
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@ -1732,7 +1730,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
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// word without having to subtract minValue. In this case,
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// we can optimize away the subtraction.
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if (cast<ConstantInt>(minValue)->getSExtValue() >= 0 &&
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cast<ConstantInt>(maxValue)->getSExtValue() <= IntPtrBits) {
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cast<ConstantInt>(maxValue)->getSExtValue() < IntPtrBits) {
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range = cast<ConstantInt>(maxValue)->getSExtValue();
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} else {
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lowBound = cast<ConstantInt>(minValue)->getSExtValue();
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@ -1757,7 +1755,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR,
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uint64_t hi = cast<ConstantInt>(I->High)->getSExtValue() - lowBound;
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for (uint64_t j = lo; j <= hi; j++) {
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CasesBits[i].Mask |= 1 << j;
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CasesBits[i].Mask |= 1ULL << j;
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CasesBits[i].Bits++;
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}
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@ -0,0 +1,160 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep '8388635' &&
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; RUN: llvm-as < %s | llc -march=x86-64 | grep '4294981120'
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; PR 1325
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; ModuleID = 'bugpoint.test.bc'
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
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target triple = "powerpc-apple-darwin8.8.0"
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;target triple = "i686-linux-gnu"
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%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
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%struct.__sFILEX = type opaque
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%struct.__sbuf = type { i8*, i32 }
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@PL_rsfp = external global %struct.FILE* ; <%struct.FILE**> [#uses=1]
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@PL_bufend = external global i8* ; <i8**> [#uses=1]
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@PL_in_eval = external global i32 ; <i32*> [#uses=1]
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declare fastcc void @incline(i8*)
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define i16 @Perl_skipspace_bb60(i8* %s, i8** %s_addr.4.out) {
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newFuncRoot:
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%tmp138.loc = alloca i8* ; <i8**> [#uses=2]
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%s_addr.4.loc = alloca i8* ; <i8**> [#uses=2]
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%tmp274.loc = alloca i8* ; <i8**> [#uses=2]
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br label %bb60
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cond_next154.UnifiedReturnBlock_crit_edge.exitStub: ; preds = %codeRepl
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store i8* %s_addr.4.reload, i8** %s_addr.4.out
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ret i16 0
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cond_next161.UnifiedReturnBlock_crit_edge.exitStub: ; preds = %codeRepl
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store i8* %s_addr.4.reload, i8** %s_addr.4.out
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ret i16 1
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cond_next167.UnifiedReturnBlock_crit_edge.exitStub: ; preds = %codeRepl
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store i8* %s_addr.4.reload, i8** %s_addr.4.out
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ret i16 2
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cond_false29.i.cond_true190_crit_edge.exitStub: ; preds = %codeRepl
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store i8* %s_addr.4.reload, i8** %s_addr.4.out
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ret i16 3
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cond_next.i.cond_true190_crit_edge.exitStub: ; preds = %codeRepl
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store i8* %s_addr.4.reload, i8** %s_addr.4.out
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ret i16 4
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cond_true19.i.cond_true190_crit_edge.exitStub: ; preds = %codeRepl
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store i8* %s_addr.4.reload, i8** %s_addr.4.out
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ret i16 5
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bb60: ; preds = %bb60.backedge, %newFuncRoot
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%s_addr.2 = phi i8* [ %s, %newFuncRoot ], [ %s_addr.2.be, %bb60.backedge ] ; <i8*> [#uses=3]
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%tmp61 = load i8** @PL_bufend ; <i8*> [#uses=1]
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%tmp63 = icmp ult i8* %s_addr.2, %tmp61 ; <i1> [#uses=1]
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br i1 %tmp63, label %bb60.cond_next67_crit_edge, label %bb60.bb101_crit_edge
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bb37: ; preds = %cond_next67.bb37_crit_edge5, %cond_next67.bb37_crit_edge4, %cond_next67.bb37_crit_edge3, %cond_next67.bb37_crit_edge2, %cond_next67.bb37_crit_edge
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%tmp40 = icmp eq i8 %tmp69, 10 ; <i1> [#uses=1]
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%tmp43 = getelementptr i8* %s_addr.27.2, i32 1 ; <i8*> [#uses=5]
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br i1 %tmp40, label %cond_true45, label %bb37.bb60_crit_edge
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cond_true45: ; preds = %bb37
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%tmp46 = volatile load i32* @PL_in_eval ; <i32> [#uses=1]
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%tmp47 = icmp eq i32 %tmp46, 0 ; <i1> [#uses=1]
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br i1 %tmp47, label %cond_true45.bb60_crit_edge, label %cond_true50
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cond_true50: ; preds = %cond_true45
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%tmp51 = volatile load %struct.FILE** @PL_rsfp ; <%struct.FILE*> [#uses=1]
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%tmp52 = icmp eq %struct.FILE* %tmp51, null ; <i1> [#uses=1]
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br i1 %tmp52, label %cond_true55, label %cond_true50.bb60_crit_edge
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cond_true55: ; preds = %cond_true50
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tail call fastcc void @incline( i8* %tmp43 )
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br label %bb60.backedge
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cond_next67: ; preds = %Perl_newSV.exit.cond_next67_crit_edge, %cond_true148.cond_next67_crit_edge, %bb60.cond_next67_crit_edge
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%s_addr.27.2 = phi i8* [ %s_addr.2, %bb60.cond_next67_crit_edge ], [ %tmp274.reload, %Perl_newSV.exit.cond_next67_crit_edge ], [ %tmp138.reload, %cond_true148.cond_next67_crit_edge ] ; <i8*> [#uses=3]
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%tmp69 = load i8* %s_addr.27.2 ; <i8> [#uses=2]
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switch i8 %tmp69, label %cond_next67.bb101_crit_edge [
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i8 32, label %cond_next67.bb37_crit_edge
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i8 9, label %cond_next67.bb37_crit_edge2
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i8 10, label %cond_next67.bb37_crit_edge3
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i8 13, label %cond_next67.bb37_crit_edge4
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i8 12, label %cond_next67.bb37_crit_edge5
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]
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codeRepl: ; preds = %bb101.preheader
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%targetBlock = call i16 @Perl_skipspace_bb60_bb101( i8* %s_addr.27.3.ph, i8** %tmp274.loc, i8** %s_addr.4.loc, i8** %tmp138.loc ) ; <i16> [#uses=1]
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%tmp274.reload = load i8** %tmp274.loc ; <i8*> [#uses=4]
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%s_addr.4.reload = load i8** %s_addr.4.loc ; <i8*> [#uses=6]
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%tmp138.reload = load i8** %tmp138.loc ; <i8*> [#uses=1]
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switch i16 %targetBlock, label %cond_true19.i.cond_true190_crit_edge.exitStub [
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i16 0, label %cond_next271.bb60_crit_edge
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i16 1, label %cond_true290.bb60_crit_edge
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i16 2, label %cond_true295.bb60_crit_edge
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i16 3, label %Perl_newSV.exit.cond_next67_crit_edge
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i16 4, label %cond_true148.cond_next67_crit_edge
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i16 5, label %cond_next154.UnifiedReturnBlock_crit_edge.exitStub
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i16 6, label %cond_next161.UnifiedReturnBlock_crit_edge.exitStub
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i16 7, label %cond_next167.UnifiedReturnBlock_crit_edge.exitStub
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i16 8, label %cond_false29.i.cond_true190_crit_edge.exitStub
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i16 9, label %cond_next.i.cond_true190_crit_edge.exitStub
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]
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bb37.bb60_crit_edge: ; preds = %bb37
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br label %bb60.backedge
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cond_true45.bb60_crit_edge: ; preds = %cond_true45
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br label %bb60.backedge
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cond_true50.bb60_crit_edge: ; preds = %cond_true50
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br label %bb60.backedge
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bb60.cond_next67_crit_edge: ; preds = %bb60
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br label %cond_next67
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bb60.bb101_crit_edge: ; preds = %bb60
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br label %bb101.preheader
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cond_next67.bb101_crit_edge: ; preds = %cond_next67
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br label %bb101.preheader
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cond_next67.bb37_crit_edge: ; preds = %cond_next67
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br label %bb37
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cond_next67.bb37_crit_edge2: ; preds = %cond_next67
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br label %bb37
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cond_next67.bb37_crit_edge3: ; preds = %cond_next67
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br label %bb37
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cond_next67.bb37_crit_edge4: ; preds = %cond_next67
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br label %bb37
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cond_next67.bb37_crit_edge5: ; preds = %cond_next67
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br label %bb37
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cond_true148.cond_next67_crit_edge: ; preds = %codeRepl
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br label %cond_next67
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cond_next271.bb60_crit_edge: ; preds = %codeRepl
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br label %bb60.backedge
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cond_true290.bb60_crit_edge: ; preds = %codeRepl
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br label %bb60.backedge
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cond_true295.bb60_crit_edge: ; preds = %codeRepl
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br label %bb60.backedge
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Perl_newSV.exit.cond_next67_crit_edge: ; preds = %codeRepl
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br label %cond_next67
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bb101.preheader: ; preds = %cond_next67.bb101_crit_edge, %bb60.bb101_crit_edge
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%s_addr.27.3.ph = phi i8* [ %s_addr.27.2, %cond_next67.bb101_crit_edge ], [ %s_addr.2, %bb60.bb101_crit_edge ] ; <i8*> [#uses=1]
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br label %codeRepl
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bb60.backedge: ; preds = %cond_true295.bb60_crit_edge, %cond_true290.bb60_crit_edge, %cond_next271.bb60_crit_edge, %cond_true50.bb60_crit_edge, %cond_true45.bb60_crit_edge, %bb37.bb60_crit_edge, %cond_true55
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%s_addr.2.be = phi i8* [ %tmp43, %cond_true55 ], [ %tmp43, %bb37.bb60_crit_edge ], [ %tmp43, %cond_true45.bb60_crit_edge ], [ %tmp43, %cond_true50.bb60_crit_edge ], [ %tmp274.reload, %cond_next271.bb60_crit_edge ], [ %tmp274.reload, %cond_true290.bb60_crit_edge ], [ %tmp274.reload, %cond_true295.bb60_crit_edge ] ; <i8*> [#uses=1]
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br label %bb60
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}
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declare i16 @Perl_skipspace_bb60_bb101(i8*, i8**, i8**, i8**)
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