Prune utf8 chars in comments.

llvm-svn: 193512
This commit is contained in:
NAKAMURA Takumi 2013-10-28 04:07:38 +00:00
parent 0b865d445e
commit 8a0464393f
2 changed files with 5 additions and 5 deletions

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@ -1106,7 +1106,7 @@ def ShRxRyOffMemX16:
// //
// Format: SLL rx, ry, sa MIPS16e // Format: SLL rx, ry, sa MIPS16e
// Purpose: Shift Word Left Logical (Extended) // Purpose: Shift Word Left Logical (Extended)
// To execute a left-shift of a word by a fixed number of bits0 to 31 bits. // To execute a left-shift of a word by a fixed number of bits-0 to 31 bits.
// //
def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
@ -1202,7 +1202,7 @@ def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
// Format: SRA rx, ry, sa MIPS16e // Format: SRA rx, ry, sa MIPS16e
// Purpose: Shift Word Right Arithmetic (Extended) // Purpose: Shift Word Right Arithmetic (Extended)
// To execute an arithmetic right-shift of a word by a fixed // To execute an arithmetic right-shift of a word by a fixed
// number of bits1 to 8 bits. // number of bits-1 to 8 bits.
// //
def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>; def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
@ -1220,7 +1220,7 @@ def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
// Format: SRL rx, ry, sa MIPS16e // Format: SRL rx, ry, sa MIPS16e
// Purpose: Shift Word Right Logical (Extended) // Purpose: Shift Word Right Logical (Extended)
// To execute a logical right-shift of a word by a fixed // To execute a logical right-shift of a word by a fixed
// number of bits1 to 31 bits. // number of bits-1 to 31 bits.
// //
def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>; def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;

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@ -1525,8 +1525,8 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
break; break;
} }
// insert_vector_elt (build_vector elt0, , eltN), NewEltIdx, idx // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
// => build_vector elt0, …, NewEltIdx, …, eltN // => build_vector elt0, ... , NewEltIdx, ... , eltN
case ISD::INSERT_VECTOR_ELT: { case ISD::INSERT_VECTOR_ELT: {
SDValue InVec = N->getOperand(0); SDValue InVec = N->getOperand(0);
SDValue InVal = N->getOperand(1); SDValue InVal = N->getOperand(1);