forked from OSchip/llvm-project
Use tblgen'd VECTOR_SHUFFLE selection code.
llvm-svn: 26900
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@ -927,22 +927,6 @@ void PPCDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::VECTOR_SHUFFLE:
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// FIXME: This should be autogenerated from the .td file, it is here for now
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// due to bugs in tblgen.
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if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
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(Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
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PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
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SDOperand N0;
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Select(N0, N->getOperand(0));
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Result = CodeGenMap[Op] =
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SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
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getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
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N0), 0);
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return;
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}
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assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
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case ISD::SETCC:
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Result = SelectSETCC(Op);
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return;
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@ -1034,9 +1034,8 @@ def VSPLTH : VXForm_1<588, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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"vspltw $vD, $vB, $UIMM", VecPerm,
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[/*
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(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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VSPLT_shuffle_mask:$UIMM))*/]>;
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[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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VSPLT_shuffle_mask:$UIMM))]>;
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// FIXME: ALSO ADD SUPPORT FOR v4i32!
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// VX-Form Pseudo Instructions
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