forked from OSchip/llvm-project
What year is it! This file has no reason to be written in C, and has doubly no
reason to expose a global symbol 'decodeInstruction' nor to pollute the global scope with a bunch of external linkage entities (some of which conflict with others elsewhere in LLVM). This is just the initial transition to C++; more cleanups to follow. llvm-svn: 206717
This commit is contained in:
Richard Smith
parent
f54f8ff094
commit
89ee75d786
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@ -1,4 +1,4 @@
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add_llvm_library(LLVMX86Disassembler
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X86Disassembler.cpp
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X86DisassemblerDecoder.c
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X86DisassemblerDecoder.cpp
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)
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@ -37,18 +37,18 @@
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using namespace llvm;
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using namespace llvm::X86Disassembler;
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void x86DisassemblerDebug(const char *file,
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unsigned line,
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const char *s) {
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void llvm::X86Disassembler::Debug(const char *file, unsigned line,
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const char *s) {
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dbgs() << file << ":" << line << ": " << s;
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}
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const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii) {
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const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
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const void *mii) {
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const MCInstrInfo *MII = static_cast<const MCInstrInfo *>(mii);
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return MII->getName(Opcode);
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}
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#define debug(s) DEBUG(x86DisassemblerDebug(__FILE__, __LINE__, s));
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#define debug(s) DEBUG(Debug(__FILE__, __LINE__, s));
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namespace llvm {
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@ -1,17 +1,17 @@
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/*===-- X86DisassemblerDecoder.c - Disassembler decoder ------------*- C -*-===*
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*
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* The LLVM Compiler Infrastructure
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*
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* This file is distributed under the University of Illinois Open Source
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* License. See LICENSE.TXT for details.
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*
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*===----------------------------------------------------------------------===*
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*
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* This file is part of the X86 Disassembler.
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* It contains the implementation of the instruction decoder.
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* Documentation for the disassembler can be found in X86Disassembler.h.
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*
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*===----------------------------------------------------------------------===*/
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//===-- X86DisassemblerDecoder.c - Disassembler decoder -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains the implementation of the instruction decoder.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#include <stdarg.h> /* for va_*() */
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#include <stdio.h> /* for vsnprintf() */
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@ -20,13 +20,15 @@
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#include "X86DisassemblerDecoder.h"
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using namespace llvm::X86Disassembler;
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#include "X86GenDisassemblerTables.inc"
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#define TRUE 1
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#define FALSE 0
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#ifndef NDEBUG
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#define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
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#define debug(s) do { Debug(__FILE__, __LINE__, s); } while (0)
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#else
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#define debug(s) do { } while (0)
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#endif
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@ -41,7 +43,7 @@
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* an instruction with these attributes.
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*/
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static InstructionContext contextForAttrs(uint16_t attrMask) {
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return CONTEXTS_SYM[attrMask];
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return static_cast<InstructionContext>(CONTEXTS_SYM[attrMask]);
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}
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/*
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@ -792,9 +794,7 @@ static int getIDWithAttrMask(uint16_t* instructionID,
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uint16_t attrMask) {
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BOOL hasModRMExtension;
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uint16_t instructionClass;
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instructionClass = contextForAttrs(attrMask);
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InstructionContext instructionClass = contextForAttrs(attrMask);
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hasModRMExtension = modRMRequired(insn->opcodeType,
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instructionClass,
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@ -1011,9 +1011,8 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
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return 0;
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}
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specName = x86DisassemblerGetInstrName(instructionID, miiArg);
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specWithOpSizeName =
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x86DisassemblerGetInstrName(instructionIDWithOpsize, miiArg);
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specName = GetInstrName(instructionID, miiArg);
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specWithOpSizeName = GetInstrName(instructionIDWithOpsize, miiArg);
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if (is16BitEquivalent(specName, specWithOpSizeName) &&
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(insn->mode == MODE_16BIT) ^ insn->prefixPresent[0x66]) {
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@ -1077,8 +1076,8 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
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* @return - 0 if the SIB byte was successfully read; nonzero otherwise.
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*/
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static int readSIB(struct InternalInstruction* insn) {
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SIBIndex sibIndexBase = 0;
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SIBBase sibBaseBase = 0;
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SIBIndex sibIndexBase = SIB_INDEX_NONE;
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SIBBase sibBaseBase = SIB_BASE_NONE;
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uint8_t index, base;
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dbgprintf(insn, "readSIB()");
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@ -1599,20 +1598,22 @@ static int readImmediate(struct InternalInstruction* insn, uint8_t size) {
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static int readVVVV(struct InternalInstruction* insn) {
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dbgprintf(insn, "readVVVV()");
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int vvvv;
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if (insn->vectorExtensionType == TYPE_EVEX)
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insn->vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
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vvvv = vvvvFromEVEX3of4(insn->vectorExtensionPrefix[2]);
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else if (insn->vectorExtensionType == TYPE_VEX_3B)
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insn->vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
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vvvv = vvvvFromVEX3of3(insn->vectorExtensionPrefix[2]);
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else if (insn->vectorExtensionType == TYPE_VEX_2B)
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insn->vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
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vvvv = vvvvFromVEX2of2(insn->vectorExtensionPrefix[1]);
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else if (insn->vectorExtensionType == TYPE_XOP)
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insn->vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
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vvvv = vvvvFromXOP3of3(insn->vectorExtensionPrefix[2]);
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else
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return -1;
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if (insn->mode != MODE_64BIT)
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insn->vvvv &= 0x7;
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vvvv &= 0x7;
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insn->vvvv = static_cast<Reg>(vvvv);
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return 0;
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}
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@ -1629,7 +1630,8 @@ static int readMaskRegister(struct InternalInstruction* insn) {
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if (insn->vectorExtensionType != TYPE_EVEX)
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return -1;
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insn->writemask = aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]);
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insn->writemask =
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static_cast<Reg>(aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]));
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return 0;
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}
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@ -1781,14 +1783,10 @@ static int readOperands(struct InternalInstruction* insn) {
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* @return - 0 if the instruction's memory could be read; nonzero if
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* not.
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*/
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int decodeInstruction(struct InternalInstruction* insn,
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byteReader_t reader,
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const void* readerArg,
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dlog_t logger,
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void* loggerArg,
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const void* miiArg,
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uint64_t startLoc,
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DisassemblerMode mode) {
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int llvm::X86Disassembler::decodeInstruction(
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struct InternalInstruction *insn, byteReader_t reader,
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const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg,
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uint64_t startLoc, DisassemblerMode mode) {
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memset(insn, 0, sizeof(struct InternalInstruction));
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insn->reader = reader;
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/*===-- X86DisassemblerDecoderInternal.h - Disassembler decoder ---*- C -*-===*
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*
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* The LLVM Compiler Infrastructure
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*
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* This file is distributed under the University of Illinois Open Source
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* License. See LICENSE.TXT for details.
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*
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*===----------------------------------------------------------------------===*
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*
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* This file is part of the X86 Disassembler.
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* It contains the public interface of the instruction decoder.
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* Documentation for the disassembler can be found in X86Disassembler.h.
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*
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*===----------------------------------------------------------------------===*/
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//===-- X86DisassemblerDecoderInternal.h - Disassembler decoder -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains the public interface of the instruction decoder.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86DISASSEMBLERDECODER_H
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#define X86DISASSEMBLERDECODER_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define INSTRUCTION_SPECIFIER_FIELDS \
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uint16_t operands;
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#undef INSTRUCTION_SPECIFIER_FIELDS
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#undef INSTRUCTION_IDS
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namespace llvm {
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namespace X86Disassembler {
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/*
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* Accessor functions for various fields of an Intel instruction
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*/
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uint64_t startLoc,
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DisassemblerMode mode);
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/* x86DisassemblerDebug - C-accessible function for printing a message to
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* debugs()
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/* \brief Debug - Print a message to debugs()
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* @param file - The name of the file printing the debug message.
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* @param line - The line number that printed the debug message.
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* @param s - The message to print.
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*/
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void x86DisassemblerDebug(const char *file,
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unsigned line,
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const char *s);
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void Debug(const char *file, unsigned line, const char *s);
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const char *x86DisassemblerGetInstrName(unsigned Opcode, const void *mii);
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const char *GetInstrName(unsigned Opcode, const void *mii);
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#ifdef __cplusplus
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}
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#endif
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} // namespace X86Disassembler
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} // namespace llvm
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#endif
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@ -1,29 +1,27 @@
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/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
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*
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* The LLVM Compiler Infrastructure
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*
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* This file is distributed under the University of Illinois Open Source
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* License. See LICENSE.TXT for details.
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*
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*===----------------------------------------------------------------------===*
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*
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* This file is part of the X86 Disassembler.
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* It contains common definitions used by both the disassembler and the table
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* generator.
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* Documentation for the disassembler can be found in X86Disassembler.h.
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*
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*===----------------------------------------------------------------------===*/
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/*
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* This header file provides those definitions that need to be shared between
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* the decoder and the table generator in a C-friendly manner.
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*/
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//===-- X86DisassemblerDecoderCommon.h - Disassembler decoder ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler.
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// It contains common definitions used by both the disassembler and the table
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// generator.
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// Documentation for the disassembler can be found in X86Disassembler.h.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86DISASSEMBLERDECODERCOMMON_H
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#define X86DISASSEMBLERDECODERCOMMON_H
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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namespace X86Disassembler {
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#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
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#define CONTEXTS_SYM x86DisassemblerContexts
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#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
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@ -274,17 +272,17 @@ enum attributeBits {
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ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
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#define ENUM_ENTRY(n, r, d) n,
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typedef enum {
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enum InstructionContext {
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INSTRUCTION_CONTEXTS
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IC_max
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} InstructionContext;
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};
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#undef ENUM_ENTRY
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/*
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* Opcode types, which determine which decode table to use, both in the Intel
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* manual and also for the decoder.
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*/
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typedef enum {
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enum OpcodeType {
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ONEBYTE = 0,
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TWOBYTE = 1,
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THREEBYTE_38 = 2,
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@ -292,7 +290,7 @@ typedef enum {
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XOP8_MAP = 4,
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XOP9_MAP = 5,
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XOPA_MAP = 6
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} OpcodeType;
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};
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/*
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* The following structs are used for the hierarchical decode table. After
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@ -333,10 +331,10 @@ typedef uint16_t InstrUID;
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ENUM_ENTRY(MODRM_FULL)
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#define ENUM_ENTRY(n) n,
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typedef enum {
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enum ModRMDecisionType {
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MODRMTYPES
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MODRM_max
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} ModRMDecisionType;
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};
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#undef ENUM_ENTRY
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/*
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@ -356,7 +354,7 @@ struct ModRMDecision {
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* given a particular opcode.
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*/
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struct OpcodeDecision {
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struct ModRMDecision modRMDecisions[256];
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ModRMDecision modRMDecisions[256];
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};
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/*
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@ -367,7 +365,7 @@ struct OpcodeDecision {
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* entries in this table, rather than 2^(ATTR_max).
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*/
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struct ContextDecision {
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struct OpcodeDecision opcodeDecisions[IC_max];
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OpcodeDecision opcodeDecisions[IC_max];
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};
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/*
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@ -408,10 +406,10 @@ struct ContextDecision {
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ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
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#define ENUM_ENTRY(n, d) n,
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typedef enum {
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ENCODINGS
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ENCODING_max
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} OperandEncoding;
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enum OperandEncoding {
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ENCODINGS
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ENCODING_max
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};
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#undef ENUM_ENTRY
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/*
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@ -508,10 +506,10 @@ struct ContextDecision {
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ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state")
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#define ENUM_ENTRY(n, d) n,
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typedef enum {
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enum OperandType {
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TYPES
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TYPE_max
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} OperandType;
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};
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#undef ENUM_ENTRY
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/*
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@ -532,10 +530,10 @@ struct OperandSpecifier {
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ENUM_ENTRY(MODIFIER_NONE)
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#define ENUM_ENTRY(n) n,
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typedef enum {
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enum ModifierType {
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MODIFIER_TYPES
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MODIFIER_max
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} ModifierType;
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};
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#undef ENUM_ENTRY
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#define X86_MAX_OPERANDS 5
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@ -554,10 +552,13 @@ struct InstructionSpecifier {
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* are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
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* respectively.
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*/
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typedef enum {
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enum DisassemblerMode {
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MODE_16BIT,
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MODE_32BIT,
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MODE_64BIT
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} DisassemblerMode;
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};
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} // namespace X86Disassembler
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} // namespace llvm
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#endif
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