Regenerate expected result for test constant-combines.ll . NFC

llvm-svn: 303533

llvm/test/CodeGen/X86/constant-combines.ll

@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s | FileCheck %s
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
@@ -11,13 +12,20 @@ define void @PR22524({ float, float }* %arg) {
 ; it folded it to a zero too late to legalize the zero store operation. If this
 ; ever starts forming a zero store instead of movss, the test case has stopped
 ; being useful.
-; 
+;
 ; CHECK-LABEL: PR22524:
+; CHECK:       # BB#0: # %entry
+; CHECK-NEXT:    movl $0, 4(%rdi)
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    movd %eax, %xmm0
+; CHECK-NEXT:    xorps %xmm1, %xmm1
+; CHECK-NEXT:    mulss %xmm0, %xmm1
+; CHECK-NEXT:    movl $0, (%rdi)
+; CHECK-NEXT:    movss %xmm1, 4(%rdi)
+; CHECK-NEXT:    retq
 entry:
   %0 = getelementptr inbounds { float, float }, { float, float }* %arg,  i32 0, i32 1
   store float 0.000000e+00, float* %0, align 4
-; CHECK: movl $0, 4(%rdi)
-
   %1 = getelementptr inbounds { float, float }, { float, float }* %arg, i64 0,  i32 0
   %2 = bitcast float* %1 to i64*
   %3 = load i64, i64* %2, align 8
@@ -28,8 +36,6 @@ entry:
   %8 = fmul float %7, 0.000000e+00
   %9 = bitcast float* %1 to i32*
   store i32 %6, i32* %9, align 4
-; CHECK: movl $0, (%rdi)
   store float %8, float* %0, align 4
-; CHECK: movss %{{.*}}, 4(%rdi)
   ret void
 }