forked from OSchip/llvm-project
[mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions
Differential Revision: http://reviews.llvm.org/D11978 llvm-svn: 246919
This commit is contained in:
Zoran Jovanovic
parent
bb6d95fc3a
commit
89ca2b982e
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@ -317,3 +317,51 @@ class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
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let Inst{8-0} = offset;
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}
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class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> ft;
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = ft;
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let Inst{20-16} = fs;
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let Inst{15-11} = fd;
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let Inst{10} = 0;
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let Inst{9-8} = fmt;
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let Inst{7-0} = funct;
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}
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class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> ft;
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bits<5> fs;
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bits<5> fd;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = ft;
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let Inst{20-16} = fs;
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let Inst{15-11} = fd;
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let Inst{10-9} = fmt;
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let Inst{8-0} = funct;
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}
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class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
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: MMR6Arch<instr_asm>, MipsR6Inst {
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bits<5> ft;
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bits<5> fs;
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bits<32> Inst;
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let Inst{31-26} = 0b010101;
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let Inst{25-21} = ft;
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let Inst{20-16} = fs;
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let Inst{15} = 0;
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let Inst{14-13} = fmt;
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let Inst{12-6} = funct;
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let Inst{5-0} = 0b111011;
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}
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@ -110,6 +110,24 @@ class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm,
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list<Register> Defs = [RA];
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}
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/// Floating Point Instructions
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class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>;
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class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>;
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class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>;
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class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>;
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class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>;
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class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>;
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class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>;
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class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>;
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class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>;
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class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>;
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class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>;
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class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>;
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class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>;
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class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>;
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class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>;
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class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>;
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//===----------------------------------------------------------------------===//
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//
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// Operand Definitions
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@ -311,6 +329,58 @@ class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO,
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class SW_MMR6_DESC : Store<"sw", GPR32Opnd>;
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class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9gpr>;
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/// Floating Point Instructions
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class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC,
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InstrItinClass Itin, bit isComm,
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SDPatternOperator OpNode = null_frag> : HARDFLOAT {
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dag OutOperandList = (outs RC:$fd);
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dag InOperandList = (ins RC:$ft, RC:$fs);
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string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
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list<dag> Pattern = [(set RC:$fd, (OpNode RC:$fs, RC:$ft))];
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InstrItinClass Itinerary = Itin;
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bit isCommutable = isComm;
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}
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class FADD_S_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>;
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class FADD_D_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"add.d", AFGR64Opnd, II_ADD_D, 1, fadd>;
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class FSUB_S_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>;
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class FSUB_D_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"sub.d", AFGR64Opnd, II_SUB_D, 0, fsub>;
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class FMUL_S_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>;
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class FMUL_D_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"mul.d", AFGR64Opnd, II_MUL_D, 1, fmul>;
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class FDIV_S_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>;
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class FDIV_D_MMR6_DESC
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: FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>;
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class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT;
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class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT;
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class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT;
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class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT;
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class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC,
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RegisterOperand SrcRC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag>
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: HARDFLOAT, NeverHasSideEffects {
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dag OutOperandList = (outs DstRC:$ft);
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dag InOperandList = (ins SrcRC:$fs);
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string AsmString = !strconcat(instr_asm, "\t$ft, $fs");
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list<dag> Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))];
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InstrItinClass Itinerary = Itin;
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Format Form = FrmFR;
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}
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class FMOV_S_MMR6_DESC
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: FMOV_FNEG_MMR6_DESC_BASE<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>;
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class FMOV_D_MMR6_DESC
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: FMOV_FNEG_MMR6_DESC_BASE<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>;
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class FNEG_S_MMR6_DESC
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: FMOV_FNEG_MMR6_DESC_BASE<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>;
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class FNEG_D_MMR6_DESC
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: FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -388,6 +458,39 @@ let DecoderMethod = "DecodeMemMMImm16" in {
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let DecoderMethod = "DecodeMemMMImm9" in {
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def SWE_MMR6 : StdMMR6Rel, SWE_MMR6_DESC, SWE_MMR6_ENC, ISA_MICROMIPS32R6;
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}
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/// Floating Point Instructions
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def FADD_S_MMR6 : StdMMR6Rel, FADD_S_MMR6_ENC, FADD_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FADD_D_MMR6 : StdMMR6Rel, FADD_D_MMR6_ENC, FADD_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FSUB_S_MMR6 : StdMMR6Rel, FSUB_S_MMR6_ENC, FSUB_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FSUB_D_MMR6 : StdMMR6Rel, FSUB_D_MMR6_ENC, FSUB_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FMUL_S_MMR6 : StdMMR6Rel, FMUL_S_MMR6_ENC, FMUL_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FMUL_D_MMR6 : StdMMR6Rel, FMUL_D_MMR6_ENC, FMUL_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FDIV_S_MMR6 : StdMMR6Rel, FDIV_S_MMR6_ENC, FDIV_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FDIV_D_MMR6 : StdMMR6Rel, FDIV_D_MMR6_ENC, FDIV_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def MADDF_S_MMR6 : R6MMR6Rel, MADDF_S_MMR6_ENC, MADDF_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def MADDF_D_MMR6 : R6MMR6Rel, MADDF_D_MMR6_ENC, MADDF_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def MSUBF_S_MMR6 : R6MMR6Rel, MSUBF_S_MMR6_ENC, MSUBF_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def MSUBF_D_MMR6 : R6MMR6Rel, MSUBF_D_MMR6_ENC, MSUBF_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FMOV_S_MMR6 : StdMMR6Rel, FMOV_S_MMR6_ENC, FMOV_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FMOV_D_MMR6 : StdMMR6Rel, FMOV_D_MMR6_ENC, FMOV_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FNEG_S_MMR6 : StdMMR6Rel, FNEG_S_MMR6_ENC, FNEG_S_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def FNEG_D_MMR6 : StdMMR6Rel, FNEG_D_MMR6_ENC, FNEG_D_MMR6_DESC,
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ISA_MICROMIPS32R6;
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}
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//===----------------------------------------------------------------------===//
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@ -702,8 +702,10 @@ def LSA_R6 : R6MMR6Rel, LSA_R6_ENC, LSA_R6_DESC, ISA_MIPS32R6;
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def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6;
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def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
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def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
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def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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let AdditionalPredicates = [NotInMicroMips] in {
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def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAXA_S : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MAX_D : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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@ -714,8 +716,10 @@ def MIN_D : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MIN_S : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MOD : R6MMR6Rel, MOD_ENC, MOD_DESC, ISA_MIPS32R6;
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def MODU : R6MMR6Rel, MODU_ENC, MODU_DESC, ISA_MIPS32R6;
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def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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let AdditionalPredicates = [NotInMicroMips] in {
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def MSUBF_S : MSUBF_S_ENC, MSUBF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def MSUBF_D : MSUBF_D_ENC, MSUBF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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}
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def MUH : R6MMR6Rel, MUH_ENC, MUH_DESC, ISA_MIPS32R6;
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def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
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def MUL_R6 : R6MMR6Rel, MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6;
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@ -133,3 +133,35 @@
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0xf8,0xa6,0x00,0x04 # CHECK: sw $5, 4($6)
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0x60,0xa4,0xae,0x08 # CHECK: swe $5, 8($4)
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0x54 0xa4 0x18 0x30 # CHECK: add.s $f3, $f4, $f5
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0x54 0xc4 0x11 0x30 # CHECK: add.d $f2, $f4, $f6
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0x54 0xa4 0x18 0x70 # CHECK: sub.s $f3, $f4, $f5
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0x54 0xc4 0x11 0x70 # CHECK: sub.d $f2, $f4, $f6
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0x54 0xa4 0x18 0xb0 # CHECK: mul.s $f3, $f4, $f5
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0x54 0xc4 0x11 0xb0 # CHECK: mul.d $f2, $f4, $f6
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0x54 0xa4 0x18 0xf0 # CHECK: div.s $f3, $f4, $f5
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0x54 0xc4 0x11 0xf0 # CHECK: div.d $f2, $f4, $f6
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0x54 0xa4 0x19 0xb8 # CHECK: maddf.s $f3, $f4, $f5
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0x54 0xa4 0x1b 0xb8 # CHECK: maddf.d $f3, $f4, $f5
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0x54 0xa4 0x19 0xf8 # CHECK: msubf.s $f3, $f4, $f5
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0x54 0xa4 0x1b 0xf8 # CHECK: msubf.d $f3, $f4, $f5
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0x54,0xc7,0x00,0x7b # CHECK: mov.s $f6, $f7
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0x54,0x86,0x20,0x7b # CHECK: mov.d $f4, $f6
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0x54,0xc7,0x0b,0x7b # CHECK: neg.s $f6, $f7
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0x54,0x86,0x2b,0x7b # CHECK: neg.d $f4, $f6
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@ -39,3 +39,35 @@
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0x58 0x64 0x29 0x98 # CHECK: ddivu $3, $4, $5
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0x58 0x64 0x29 0xd8 # CHECK: dmodu $3, $4, $5
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0x54 0xa4 0x18 0x30 # CHECK: add.s $f3, $f4, $f5
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0x54 0xc4 0x11 0x30 # CHECK: add.d $f2, $f4, $f6
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0x54 0xa4 0x18 0x70 # CHECK: sub.s $f3, $f4, $f5
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0x54 0xc4 0x11 0x70 # CHECK: sub.d $f2, $f4, $f6
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0x54 0xa4 0x18 0xb0 # CHECK: mul.s $f3, $f4, $f5
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0x54 0xc4 0x11 0xb0 # CHECK: mul.d $f2, $f4, $f6
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0x54 0xa4 0x18 0xf0 # CHECK: div.s $f3, $f4, $f5
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0x54 0xc4 0x11 0xf0 # CHECK: div.d $f2, $f4, $f6
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0x54 0xa4 0x19 0xb8 # CHECK: maddf.s $f3, $f4, $f5
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0x54 0xa4 0x1b 0xb8 # CHECK: maddf.d $f3, $f4, $f5
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0x54 0xa4 0x19 0xf8 # CHECK: msubf.s $f3, $f4, $f5
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0x54 0xa4 0x1b 0xf8 # CHECK: msubf.d $f3, $f4, $f5
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0x54,0xc7,0x00,0x7b # CHECK: mov.s $f6, $f7
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0x54,0x86,0x20,0x7b # CHECK: mov.d $f4, $f6
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0x54,0xc7,0x0b,0x7b # CHECK: neg.s $f6, $f7
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0x54,0x86,0x2b,0x7b # CHECK: neg.d $f4, $f6
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@ -69,4 +69,20 @@
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xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
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sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
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swe $5, 8($4) # CHECK: swe $5, 8($4) # encoding: [0x60,0xa4,0xae,0x08]
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add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
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add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
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sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
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sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
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mul.s $f3, $f4, $f5 # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0]
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mul.d $f2, $f4, $f6 # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0]
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||||
div.s $f3, $f4, $f5 # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0]
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div.d $f2, $f4, $f6 # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0]
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||||
maddf.s $f3, $f4, $f5 # CHECK: maddf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xb8]
|
||||
maddf.d $f3, $f4, $f5 # CHECK: maddf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xb8]
|
||||
msubf.s $f3, $f4, $f5 # CHECK: msubf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xf8]
|
||||
msubf.d $f3, $f4, $f5 # CHECK: msubf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xf8]
|
||||
mov.s $f6, $f7 # CHECK: mov.s $f6, $f7 # encoding: [0x54,0xc7,0x00,0x7b]
|
||||
mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b]
|
||||
neg.s $f6, $f7 # CHECK: neg.s $f6, $f7 # encoding: [0x54,0xc7,0x0b,0x7b]
|
||||
neg.d $f4, $f6 # CHECK: neg.d $f4, $f6 # encoding: [0x54,0x86,0x2b,0x7b]
|
||||
|
||||
|
|
|
|||
|
|
@ -21,5 +21,21 @@ a:
|
|||
dmod $3, $4, $5 # CHECK: dmod $3, $4, $5 # encoding: [0x58,0x64,0x29,0x58]
|
||||
ddivu $3, $4, $5 # CHECK: ddivu $3, $4, $5 # encoding: [0x58,0x64,0x29,0x98]
|
||||
dmodu $3, $4, $5 # CHECK: dmodu $3, $4, $5 # encoding: [0x58,0x64,0x29,0xd8]
|
||||
add.s $f3, $f4, $f5 # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
|
||||
add.d $f2, $f4, $f6 # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
|
||||
sub.s $f3, $f4, $f5 # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
|
||||
sub.d $f2, $f4, $f6 # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
|
||||
mul.s $f3, $f4, $f5 # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0]
|
||||
mul.d $f2, $f4, $f6 # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0]
|
||||
div.s $f3, $f4, $f5 # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0]
|
||||
div.d $f2, $f4, $f6 # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0]
|
||||
maddf.s $f3, $f4, $f5 # CHECK: maddf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xb8]
|
||||
maddf.d $f3, $f4, $f5 # CHECK: maddf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xb8]
|
||||
msubf.s $f3, $f4, $f5 # CHECK: msubf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xf8]
|
||||
msubf.d $f3, $f4, $f5 # CHECK: msubf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xf8]
|
||||
mov.s $f6, $f7 # CHECK: mov.s $f6, $f7 # encoding: [0x54,0xc7,0x00,0x7b]
|
||||
mov.d $f4, $f6 # CHECK: mov.d $f4, $f6 # encoding: [0x54,0x86,0x20,0x7b]
|
||||
neg.s $f6, $f7 # CHECK: neg.s $f6, $f7 # encoding: [0x54,0xc7,0x0b,0x7b]
|
||||
neg.d $f4, $f6 # CHECK: neg.d $f4, $f6 # encoding: [0x54,0x86,0x2b,0x7b]
|
||||
|
||||
1:
|
||||
|
|
|
|||
Loading…
Reference in New Issue