From 89b7091c28ad7879aea5d463930f54e7a9ba236e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 25 Jan 2020 14:17:16 -0500 Subject: [PATCH] AMDGPU: Make LDS_DIRECT an artifical register --- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index 7e4320b48f6a..558e964ec3f0 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -131,7 +131,12 @@ def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>; def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>; def SRC_POPS_EXITING_WAVE_ID : SIReg<"src_pops_exiting_wave_id", 239>; -def LDS_DIRECT : SIReg <"src_lds_direct", 254>; +def LDS_DIRECT : SIReg <"src_lds_direct", 254> { + // There is no physical register corresponding to this. This is an + // encoding value in a source field, which will ultimately trigger a + // read from m0. + let isArtificial = 1; +} def XNACK_MASK_LO : SIReg<"xnack_mask_lo", 104>; def XNACK_MASK_HI : SIReg<"xnack_mask_hi", 105>; @@ -422,7 +427,7 @@ def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32, let CopyCost = -1; } -def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, +def LDS_DIRECT_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add LDS_DIRECT)> { let isAllocatable = 0; let CopyCost = -1; @@ -454,8 +459,8 @@ def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32 let AllocationPriority = 10; } -def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16, i1], 32, - (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI, SReg_32_XEXEC_HI, LDS_DIRECT_CLASS)> { +def SRegOrLds_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32, + (add SReg_32, LDS_DIRECT_CLASS)> { let isAllocatable = 0; }