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AMDGPU/R600: Cleanup DAGCombine 

Move SDLoc initialization to comon place.
fall back to AMDGPU version in one place

Differential Revision: https://reviews.llvm.org/D23900

llvm-svn: 280030
This commit is contained in:
Jan Vesely 2016-08-29 23:21:46 +00:00
parent 9848c3656c
commit 89876673cd
1 changed files with 12 additions and 15 deletions
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27
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
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@ -1706,14 +1706,14 @@ SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4],
SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
SDLoc DL(N);
switch (N->getOpcode()) {
default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
// (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
case ISD::FP_ROUND: {
SDValue Arg = N->getOperand(0);
if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), N->getValueType(0),
return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0),
Arg.getOperand(0));
}
break;
@ -1738,12 +1738,11 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
return SDValue();
}
SDLoc dl(N);
return DAG.getNode(ISD::SELECT_CC, dl, N->getValueType(0),
return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0),
SelectCC.getOperand(0), // LHS
SelectCC.getOperand(1), // RHS
DAG.getConstant(-1, dl, MVT::i32), // True
DAG.getConstant(0, dl, MVT::i32), // False
DAG.getConstant(-1, DL, MVT::i32), // True
DAG.getConstant(0, DL, MVT::i32), // False
SelectCC.getOperand(4)); // CC
break;
@ -1755,7 +1754,6 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
SDValue InVec = N->getOperand(0);
SDValue InVal = N->getOperand(1);
SDValue EltNo = N->getOperand(2);
SDLoc dl(N);
// If the inserted element is an UNDEF, just use the input vector.
if (InVal.isUndef())
@ -1793,13 +1791,13 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
EVT OpVT = Ops[0].getValueType();
if (InVal.getValueType() != OpVT)
InVal = OpVT.bitsGT(InVal.getValueType()) ?
DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) :
DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal);
Ops[Elt] = InVal;
}
// Return the new vector
return DAG.getBuildVector(VT, dl, Ops);
return DAG.getBuildVector(VT, DL, Ops);
}
// Extract_vec (Build_vector) generated by custom lowering
@ -1816,8 +1814,8 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
unsigned Element = Const->getZExtValue();
return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getVTList(),
Arg->getOperand(0).getOperand(Element));
return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
Arg->getOperand(0).getOperand(Element));
}
}
break;
@ -1858,7 +1856,7 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
LHS.getOperand(0).getValueType().isInteger());
if (DCI.isBeforeLegalizeOps() ||
isCondCodeLegal(LHSCC, LHS.getOperand(0).getSimpleValueType()))
return DAG.getSelectCC(SDLoc(N),
return DAG.getSelectCC(DL,
LHS.getOperand(0),
LHS.getOperand(1),
LHS.getOperand(2),
@ -1885,7 +1883,6 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
N->getOperand(6), // SWZ_Z
N->getOperand(7) // SWZ_W
};
SDLoc DL(N);
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL);
return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs);
}
@ -1915,10 +1912,10 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
N->getOperand(17),
N->getOperand(18),
};
SDLoc DL(N);
NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL);
return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs);
}
default: break;
}
return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);