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AMDGPU: Remove unused intrinsics 

llvm-svn: 275371
This commit is contained in:
Matt Arsenault 2016-07-14 05:23:19 +00:00
parent aa94c1e7ee
commit 897eee4187
3 changed files with 0 additions and 119 deletions
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4
llvm/lib/Target/AMDGPU/AMDGPUIntrinsics.td
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@ -16,10 +16,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
def int_AMDGPU_kilp : Intrinsic<[], [], []>;
def int_AMDGPU_cvt_f32_ubyte0 : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_cvt_f32_ubyte1 : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_cvt_f32_ubyte2 : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_cvt_f32_ubyte3 : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrNoMem]>;
def int_AMDGPU_flbit_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
// Deprecated in favor of separate int_amdgcn_cube* intrinsics.

8
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -1911,14 +1911,6 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
Denominator, Numerator);
}
case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
default:
return AMDGPUTargetLowering::LowerOperation(Op, DAG);
}

107
llvm/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll
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@ -1,107 +0,0 @@
; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
declare float @llvm.AMDGPU.cvt.f32.ubyte0(i32) nounwind readnone
declare float @llvm.AMDGPU.cvt.f32.ubyte1(i32) nounwind readnone
declare float @llvm.AMDGPU.cvt.f32.ubyte2(i32) nounwind readnone
declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone
; SI-LABEL: {{^}}test_unpack_byte0_to_float:
; SI: v_cvt_f32_ubyte0
define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: {{^}}test_unpack_byte1_to_float:
; SI: v_cvt_f32_ubyte1
define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: {{^}}test_unpack_byte2_to_float:
; SI: v_cvt_f32_ubyte2
define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: {{^}}test_unpack_byte3_to_float:
; SI: v_cvt_f32_ubyte3
define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: {{^}}byte1_shift8:
; SI: buffer_load_dword [[VAL:v[0-9]+]]
; SI-NOT: [[VAL]]
; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]]
; SI: buffer_store_dword [[CONV]]
define void @byte1_shift8(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%shift = lshr i32 %val, 8
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: {{^}}byte1_shift7:
; SI: buffer_load_dword [[VAL:v[0-9]+]]
; SI: v_lshrrev_b32_e32 [[SRL:v[0-9]+]], 7, [[VAL]]
; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[SRL]]
; SI: buffer_store_dword [[CONV]]
define void @byte1_shift7(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%shift = lshr i32 %val, 7
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: {{^}}byte1_shift16:
; SI: buffer_load_dword [[VAL:v[0-9]+]]
; SI-NOT: [[VAL]]
; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]]
; SI: buffer_store_dword [[CONV]]
define void @byte1_shift16(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%shift = lshr i32 %val, 16
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; SI-LABEL: {{^}}byte2_shift8:
; SI: buffer_load_dword [[VAL:v[0-9]+]]
; SI-NOT: [[VAL]]
; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]]
; SI: buffer_store_dword [[CONV]]
define void @byte2_shift8(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%shift = lshr i32 %val, 8
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %shift) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}
; XXX - undef
; SI-LABEL: {{^}}byte1_shift24:
; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], 0
; SI: buffer_store_dword [[CONV]]
define void @byte1_shift24(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%val = load i32, i32 addrspace(1)* %in, align 4
%shift = lshr i32 %val, 24
%cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %shift) nounwind readnone
store float %cvt, float addrspace(1)* %out, align 4
ret void
}