forked from OSchip/llvm-project
[StructurizeCFG] Fix region nodes ordering
This is a reimplementation of the `orderNodes` function, as the old implementation didn't take into account all cases. Fix PR41509 Differential Revision: https://reviews.llvm.org/D79037
This commit is contained in:
Ehud Katz
parent
f61f6ffe11
commit
897d8ee5cd
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@ -215,7 +215,6 @@ class StructurizeCFG : public RegionPass {
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void orderNodes();
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Loop *getAdjustedLoop(RegionNode *RN);
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unsigned getAdjustedLoopDepth(RegionNode *RN);
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void analyzeLoops(RegionNode *N);
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@ -324,65 +323,108 @@ Loop *StructurizeCFG::getAdjustedLoop(RegionNode *RN) {
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return LI->getLoopFor(RN->getEntry());
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}
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/// Use the exit block to determine the loop depth if RN is a SubRegion.
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unsigned StructurizeCFG::getAdjustedLoopDepth(RegionNode *RN) {
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if (RN->isSubRegion()) {
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Region *SubR = RN->getNodeAs<Region>();
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return LI->getLoopDepth(SubR->getExit());
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}
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return LI->getLoopDepth(RN->getEntry());
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}
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/// Build up the general order of nodes
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/// Build up the general order of nodes, by performing a topology sort of the
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/// parent region's nodes, while ensuring that there is no outer loop node
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/// between any two inner loop nodes.
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void StructurizeCFG::orderNodes() {
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ReversePostOrderTraversal<Region*> RPOT(ParentRegion);
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SmallDenseMap<Loop*, unsigned, 8> LoopBlocks;
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SmallVector<RegionNode *, 32> POT;
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SmallDenseMap<Loop *, unsigned, 8> LoopSizes;
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for (RegionNode *RN : post_order(ParentRegion)) {
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POT.push_back(RN);
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// The reverse post-order traversal of the list gives us an ordering close
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// to what we want. The only problem with it is that sometimes backedges
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// for outer loops will be visited before backedges for inner loops.
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for (RegionNode *RN : RPOT) {
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// Accumulate the number of nodes inside the region that belong to a loop.
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Loop *Loop = getAdjustedLoop(RN);
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++LoopBlocks[Loop];
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++LoopSizes[Loop];
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}
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// A quick exit for the case where all nodes belong to the same loop (or no
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// loop at all).
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if (LoopSizes.size() <= 1U) {
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Order.assign(POT.begin(), POT.end());
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return;
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}
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Order.resize(POT.size());
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unsigned CurrentLoopDepth = 0;
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// The post-order traversal of the list gives us an ordering close to what we
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// want. The only problem with it is that sometimes backedges for outer loops
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// will be visited before backedges for inner loops. So now we fix that by
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// inserting the nodes in order, while making sure that encountered inner loop
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// are complete before their parents (outer loops).
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SmallVector<Loop *, 8> WorkList;
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// Get the size of the outermost region (the nodes that don't belong to any
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// loop inside ParentRegion).
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unsigned ZeroCurrentLoopSize = 0U;
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auto LSI = LoopSizes.find(nullptr);
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unsigned *CurrentLoopSize =
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LSI != LoopSizes.end() ? &LSI->second : &ZeroCurrentLoopSize;
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Loop *CurrentLoop = nullptr;
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for (auto I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
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RegionNode *RN = cast<RegionNode>(*I);
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unsigned LoopDepth = getAdjustedLoopDepth(RN);
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if (is_contained(Order, *I))
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continue;
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// The "skipped" list is actually located at the (reversed) beginning of the
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// POT. This saves us the use of an intermediate container.
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// Note that there is always enough room, for the skipped nodes, before the
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// current location, as we have just passed at least that amount of nodes.
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if (LoopDepth < CurrentLoopDepth) {
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// Make sure we have visited all blocks in this loop before moving back to
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// the outer loop.
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auto LoopI = I;
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while (unsigned &BlockCount = LoopBlocks[CurrentLoop]) {
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LoopI++;
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if (getAdjustedLoop(cast<RegionNode>(*LoopI)) == CurrentLoop) {
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--BlockCount;
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Order.push_back(*LoopI);
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}
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}
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auto Begin = POT.rbegin();
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auto I = Begin, SkippedEnd = Begin;
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auto O = Order.rbegin(), OE = Order.rend();
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while (O != OE) {
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// If we have any skipped nodes, then erase the gap between the end of the
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// "skipped" list, and the current location.
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if (SkippedEnd != Begin) {
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POT.erase(I.base(), SkippedEnd.base());
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I = SkippedEnd = Begin = POT.rbegin();
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}
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CurrentLoop = getAdjustedLoop(RN);
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if (CurrentLoop)
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LoopBlocks[CurrentLoop]--;
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// Keep processing outer loops, in order (from inner most, to outer).
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if (!WorkList.empty()) {
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CurrentLoop = WorkList.pop_back_val();
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CurrentLoopSize = &LoopSizes.find(CurrentLoop)->second;
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}
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CurrentLoopDepth = LoopDepth;
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Order.push_back(*I);
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// Keep processing loops while only going deeper (into inner loops).
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do {
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assert(I != POT.rend());
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RegionNode *RN = *I++;
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Loop *L = getAdjustedLoop(RN);
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if (L != CurrentLoop) {
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// If L is a loop inside CurrentLoop, then CurrentLoop must be the
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// parent of L.
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// To prove this, we will contradict the opposite:
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// Let P be the parent of L. If CurrentLoop is the parent of P, then
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// the header of P must have been processed already, as it must
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// dominate the other blocks of P (otherwise P is an irreducible loop,
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// and won't be recorded in the LoopInfo), especially L (inside). But
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// then CurrentLoop must have been updated to P at the time of
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// processing the header of P, which conflicts with the assumption
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// that CurrentLoop is not P.
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// If L is not a loop inside CurrentLoop, then skip RN.
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if (!L || L->getParentLoop() != CurrentLoop) {
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// Skip the node by pushing it to the end of the "skipped" list.
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*SkippedEnd++ = RN;
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continue;
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}
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// If we still haven't processed all the nodes that belong to
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// CurrentLoop, then make sure we come back later, to finish the job, by
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// pushing it to the WorkList.
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if (*CurrentLoopSize)
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WorkList.push_back(CurrentLoop);
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CurrentLoop = L;
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CurrentLoopSize = &LoopSizes.find(CurrentLoop)->second;
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}
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assert(O != OE);
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*O++ = RN;
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// If we have finished processing the current loop, then we are done here.
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--*CurrentLoopSize;
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} while (*CurrentLoopSize);
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}
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// This pass originally used a post-order traversal and then operated on
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// the list in reverse. Now that we are using a reverse post-order traversal
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// rather than re-working the whole pass to operate on the list in order,
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// we just reverse the list and continue to operate on it in reverse.
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std::reverse(Order.begin(), Order.end());
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assert(WorkList.empty());
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assert(SkippedEnd == Begin);
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}
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/// Determine the end of the loops
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@ -0,0 +1,262 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -structurizecfg %s -o - | FileCheck %s
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; This test have an outer loop containing an inner loop,
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; for which there is an interleaved post-order traversal.
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;
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; This used to produce incorrect code.
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; For example %outer.loop.body used to branched to %inner.loop.end
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; (instead of %inner.loop.header).
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define i1 @test_nested(i32 %x, i1 %b1, i1 %b2, i1 %b3) {
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; CHECK-LABEL: @test_nested(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[B3_INV:%.*]] = xor i1 [[B3:%.*]], true
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; CHECK-NEXT: br label [[OUTER_LOOP_HEADER:%.*]]
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; CHECK: Flow12:
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; CHECK-NEXT: br i1 [[TMP3:%.*]], label [[EXIT_TRUE:%.*]], label [[FLOW13:%.*]]
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; CHECK: exit.true:
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; CHECK-NEXT: br label [[FLOW13]]
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; CHECK: Flow13:
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; CHECK-NEXT: br i1 [[TMP2:%.*]], label [[NEWDEFAULT:%.*]], label [[FLOW14:%.*]]
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; CHECK: NewDefault:
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; CHECK-NEXT: br label [[EXIT_FALSE:%.*]]
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; CHECK: Flow14:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ false, [[EXIT_FALSE]] ], [ true, [[FLOW13]] ]
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: exit.false:
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; CHECK-NEXT: br label [[FLOW14]]
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; CHECK: outer.loop.header:
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; CHECK-NEXT: br i1 [[B1:%.*]], label [[OUTER_LOOP_BODY:%.*]], label [[FLOW3:%.*]]
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; CHECK: outer.loop.body:
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; CHECK-NEXT: br label [[INNER_LOOP_HEADER:%.*]]
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; CHECK: Flow3:
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; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP16:%.*]], [[FLOW11:%.*]] ], [ true, [[OUTER_LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP2]] = phi i1 [ [[TMP12:%.*]], [[FLOW11]] ], [ false, [[OUTER_LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP3]] = phi i1 [ false, [[FLOW11]] ], [ true, [[OUTER_LOOP_HEADER]] ]
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; CHECK-NEXT: br i1 [[TMP1]], label [[FLOW12:%.*]], label [[OUTER_LOOP_HEADER]]
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; CHECK: inner.loop.header:
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; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ [[TMP8:%.*]], [[FLOW4:%.*]] ], [ false, [[OUTER_LOOP_BODY]] ]
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; CHECK-NEXT: br i1 [[B2:%.*]], label [[INNER_LOOP_BODY:%.*]], label [[FLOW4]]
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; CHECK: Flow6:
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; CHECK-NEXT: [[TMP5:%.*]] = phi i1 [ false, [[INNER_LOOP_LATCH:%.*]] ], [ true, [[LEAFBLOCK:%.*]] ]
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; CHECK-NEXT: br label [[FLOW5:%.*]]
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; CHECK: Flow7:
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; CHECK-NEXT: br i1 [[TMP10:%.*]], label [[INNER_LOOP_END:%.*]], label [[FLOW8:%.*]]
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; CHECK: inner.loop.end:
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; CHECK-NEXT: br label [[FLOW8]]
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; CHECK: inner.loop.body:
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; CHECK-NEXT: br i1 [[B3_INV]], label [[INNER_LOOP_BODY_ELSE:%.*]], label [[FLOW:%.*]]
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; CHECK: inner.loop.body.else:
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP6:%.*]] = phi i1 [ false, [[INNER_LOOP_BODY_ELSE]] ], [ true, [[INNER_LOOP_BODY]] ]
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; CHECK-NEXT: br i1 [[TMP6]], label [[INNER_LOOP_BODY_THEN:%.*]], label [[INNER_LOOP_COND:%.*]]
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; CHECK: inner.loop.body.then:
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; CHECK-NEXT: br label [[INNER_LOOP_COND]]
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; CHECK: Flow4:
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; CHECK-NEXT: [[TMP7:%.*]] = phi i1 [ [[TMP17:%.*]], [[FLOW5]] ], [ true, [[INNER_LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP8]] = phi i1 [ [[TMP18:%.*]], [[FLOW5]] ], [ [[TMP4]], [[INNER_LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP9:%.*]] = phi i1 [ [[TMP19:%.*]], [[FLOW5]] ], [ false, [[INNER_LOOP_HEADER]] ]
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; CHECK-NEXT: [[TMP10]] = phi i1 [ false, [[FLOW5]] ], [ true, [[INNER_LOOP_HEADER]] ]
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; CHECK-NEXT: br i1 [[TMP7]], label [[FLOW7:%.*]], label [[INNER_LOOP_HEADER]]
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; CHECK: inner.loop.cond:
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; CHECK-NEXT: br label [[NODEBLOCK:%.*]]
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; CHECK: NodeBlock:
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; CHECK-NEXT: [[PIVOT:%.*]] = icmp slt i32 [[X:%.*]], 1
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; CHECK-NEXT: br i1 [[PIVOT]], label [[LEAFBLOCK]], label [[FLOW5]]
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; CHECK: Flow8:
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; CHECK-NEXT: [[TMP11:%.*]] = phi i1 [ true, [[INNER_LOOP_END]] ], [ false, [[FLOW7]] ]
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; CHECK-NEXT: br i1 [[TMP9]], label [[LEAFBLOCK1:%.*]], label [[FLOW9:%.*]]
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; CHECK: LeafBlock1:
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; CHECK-NEXT: [[SWITCHLEAF2:%.*]] = icmp eq i32 [[X]], 1
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; CHECK-NEXT: br i1 [[SWITCHLEAF2]], label [[INNER_LOOP_BREAK:%.*]], label [[FLOW10:%.*]]
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; CHECK: LeafBlock:
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; CHECK-NEXT: [[SWITCHLEAF:%.*]] = icmp eq i32 [[X]], 0
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; CHECK-NEXT: br i1 [[SWITCHLEAF]], label [[INNER_LOOP_LATCH]], label [[FLOW6:%.*]]
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; CHECK: Flow9:
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; CHECK-NEXT: [[TMP12]] = phi i1 [ [[TMP14:%.*]], [[FLOW10]] ], [ [[TMP8]], [[FLOW8]] ]
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; CHECK-NEXT: [[TMP13:%.*]] = phi i1 [ [[TMP15:%.*]], [[FLOW10]] ], [ [[TMP11]], [[FLOW8]] ]
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; CHECK-NEXT: br i1 [[TMP13]], label [[OUTER_LOOP_CLEANUP:%.*]], label [[FLOW11]]
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; CHECK: inner.loop.break:
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; CHECK-NEXT: br label [[FLOW10]]
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; CHECK: Flow10:
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; CHECK-NEXT: [[TMP14]] = phi i1 [ false, [[INNER_LOOP_BREAK]] ], [ true, [[LEAFBLOCK1]] ]
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; CHECK-NEXT: [[TMP15]] = phi i1 [ true, [[INNER_LOOP_BREAK]] ], [ [[TMP11]], [[LEAFBLOCK1]] ]
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; CHECK-NEXT: br label [[FLOW9]]
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; CHECK: outer.loop.cleanup:
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; CHECK-NEXT: br label [[OUTER_LOOP_LATCH:%.*]]
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; CHECK: Flow11:
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; CHECK-NEXT: [[TMP16]] = phi i1 [ false, [[OUTER_LOOP_LATCH]] ], [ true, [[FLOW9]] ]
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; CHECK-NEXT: br label [[FLOW3]]
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; CHECK: outer.loop.latch:
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; CHECK-NEXT: br label [[FLOW11]]
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; CHECK: Flow5:
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; CHECK-NEXT: [[TMP17]] = phi i1 [ [[TMP5]], [[FLOW6]] ], [ true, [[NODEBLOCK]] ]
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; CHECK-NEXT: [[TMP18]] = phi i1 [ [[TMP5]], [[FLOW6]] ], [ [[TMP4]], [[NODEBLOCK]] ]
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; CHECK-NEXT: [[TMP19]] = phi i1 [ false, [[FLOW6]] ], [ true, [[NODEBLOCK]] ]
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; CHECK-NEXT: br label [[FLOW4]]
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; CHECK: inner.loop.latch:
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; CHECK-NEXT: br label [[FLOW6]]
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; CHECK: exit:
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; CHECK-NEXT: ret i1 [[TMP0]]
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;
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entry:
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br label %outer.loop.header
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exit.true: ; preds = %outer.loop.header
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br label %exit
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exit.false: ; preds = %inner.loop.cond
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br label %exit
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outer.loop.header: ; preds = %outer.loop.latch, %entry
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br i1 %b1, label %outer.loop.body, label %exit.true
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outer.loop.body: ; preds = %outer.loop.header
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br label %inner.loop.header
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inner.loop.header: ; preds = %inner.loop.latch, %outer.loop.body
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br i1 %b2, label %inner.loop.body, label %inner.loop.end
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inner.loop.end: ; preds = %inner.loop.header
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br label %outer.loop.cleanup
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inner.loop.body: ; preds = %inner.loop.header
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br i1 %b3, label %inner.loop.body.then, label %inner.loop.body.else
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inner.loop.body.else: ; preds = %inner.loop.body
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br label %inner.loop.cond
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inner.loop.body.then: ; preds = %inner.loop.body
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br label %inner.loop.cond
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inner.loop.cond: ; preds = %inner.loop.body.then, %inner.loop.body.else
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switch i32 %x, label %exit.false [
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i32 0, label %inner.loop.latch
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i32 1, label %inner.loop.break
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]
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inner.loop.break: ; preds = %inner.loop.cond
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br label %outer.loop.cleanup
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outer.loop.cleanup: ; preds = %inner.loop.break, %inner.loop.end
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br label %outer.loop.latch
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outer.loop.latch: ; preds = %outer.loop.cleanup
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br label %outer.loop.header
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inner.loop.latch: ; preds = %inner.loop.cond
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br label %inner.loop.header
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exit: ; preds = %exit.false, %exit.true
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%r = phi i1 [ true, %exit.true ], [ false, %exit.false ]
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ret i1 %r
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}
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; This test checks sibling loops that by default have an
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; interleaved post-order traversal.
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define void @test_siblings(i1 %b1, i1 %b2, i1 %b3, i1 %b4, i1 %b5, i1 %b6, i1 %b7, i1 %b8, i1 %b9) {
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; CHECK-LABEL: @test_siblings(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[B9_INV:%.*]] = xor i1 [[B9:%.*]], true
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; CHECK-NEXT: [[B6_INV:%.*]] = xor i1 [[B6:%.*]], true
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; CHECK-NEXT: [[B2_INV:%.*]] = xor i1 [[B2:%.*]], true
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; CHECK-NEXT: [[B8_INV:%.*]] = xor i1 [[B8:%.*]], true
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; CHECK-NEXT: [[B5_INV:%.*]] = xor i1 [[B5:%.*]], true
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; CHECK-NEXT: [[B3_INV:%.*]] = xor i1 [[B3:%.*]], true
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; CHECK-NEXT: [[B4_INV:%.*]] = xor i1 [[B4:%.*]], true
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; CHECK-NEXT: [[B1_INV:%.*]] = xor i1 [[B1:%.*]], true
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; CHECK-NEXT: br i1 [[B1_INV]], label [[IF_ELSE:%.*]], label [[FLOW:%.*]]
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; CHECK: if.else:
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; CHECK-NEXT: br label [[FLOW]]
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; CHECK: Flow:
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; CHECK-NEXT: [[TMP0:%.*]] = phi i1 [ [[TMP0]], [[FLOW1:%.*]] ], [ [[B2]], [[IF_ELSE]] ], [ false, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP5:%.*]], [[FLOW1]] ], [ [[B2_INV]], [[IF_ELSE]] ], [ false, [[ENTRY]] ]
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; CHECK-NEXT: [[TMP2:%.*]] = phi i1 [ false, [[FLOW1]] ], [ false, [[IF_ELSE]] ], [ true, [[ENTRY]] ]
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; CHECK-NEXT: br i1 [[TMP2]], label [[LOOP1_HEADER:%.*]], label [[FLOW1]]
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; CHECK: loop1.header:
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; CHECK-NEXT: br i1 [[B3_INV]], label [[LOOP1_BODY:%.*]], label [[FLOW2:%.*]]
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; CHECK: Flow2:
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; CHECK-NEXT: [[TMP3:%.*]] = phi i1 [ true, [[LOOP1_BODY]] ], [ [[TMP1]], [[LOOP1_HEADER]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = phi i1 [ [[B5_INV]], [[LOOP1_BODY]] ], [ [[B3]], [[LOOP1_HEADER]] ]
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; CHECK-NEXT: br i1 [[TMP4]], label [[LOOP1_LATCH:%.*]], label [[FLOW3:%.*]]
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; CHECK: loop1.latch:
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; CHECK-NEXT: br label [[FLOW3]]
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; CHECK: Flow1:
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; CHECK-NEXT: [[TMP5]] = phi i1 [ [[TMP6:%.*]], [[FLOW3]] ], [ [[TMP1]], [[FLOW]] ]
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; CHECK-NEXT: br i1 true, label [[FLOW4:%.*]], label [[FLOW]]
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; CHECK: loop1.body:
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; CHECK-NEXT: br label [[FLOW2]]
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; CHECK: Flow3:
|
||||
; CHECK-NEXT: [[TMP6]] = phi i1 [ false, [[LOOP1_LATCH]] ], [ [[TMP3]], [[FLOW2]] ]
|
||||
; CHECK-NEXT: br label [[FLOW1]]
|
||||
; CHECK: Flow4:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = phi i1 [ false, [[FLOW5:%.*]] ], [ [[TMP5]], [[FLOW1]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP7]], label [[LOOP2_HEADER:%.*]], label [[FLOW5]]
|
||||
; CHECK: loop2.header:
|
||||
; CHECK-NEXT: br i1 [[B6_INV]], label [[LOOP2_BODY:%.*]], label [[FLOW6:%.*]]
|
||||
; CHECK: Flow5:
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = phi i1 [ [[TMP11:%.*]], [[FLOW7:%.*]] ], [ false, [[FLOW4]] ]
|
||||
; CHECK-NEXT: br i1 true, label [[FLOW8:%.*]], label [[FLOW4]]
|
||||
; CHECK: loop2.body:
|
||||
; CHECK-NEXT: br label [[FLOW6]]
|
||||
; CHECK: Flow6:
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = phi i1 [ true, [[LOOP2_BODY]] ], [ false, [[LOOP2_HEADER]] ]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = phi i1 [ [[B7:%.*]], [[LOOP2_BODY]] ], [ [[B6]], [[LOOP2_HEADER]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP10]], label [[LOOP2_LATCH:%.*]], label [[FLOW7]]
|
||||
; CHECK: loop2.latch:
|
||||
; CHECK-NEXT: br label [[FLOW7]]
|
||||
; CHECK: Flow7:
|
||||
; CHECK-NEXT: [[TMP11]] = phi i1 [ false, [[LOOP2_LATCH]] ], [ [[TMP9]], [[FLOW6]] ]
|
||||
; CHECK-NEXT: br label [[FLOW5]]
|
||||
; CHECK: Flow8:
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = phi i1 [ false, [[FLOW10:%.*]] ], [ [[TMP0]], [[FLOW5]] ]
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = phi i1 [ false, [[FLOW10]] ], [ [[TMP8]], [[FLOW5]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP13]], label [[LOOP3_HEADER:%.*]], label [[FLOW9:%.*]]
|
||||
; CHECK: loop3.header:
|
||||
; CHECK-NEXT: br label [[FLOW9]]
|
||||
; CHECK: Flow9:
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = phi i1 [ true, [[LOOP3_HEADER]] ], [ [[TMP12]], [[FLOW8]] ]
|
||||
; CHECK-NEXT: br i1 [[TMP14]], label [[LOOP3_LATCH:%.*]], label [[FLOW10]]
|
||||
; CHECK: loop3.latch:
|
||||
; CHECK-NEXT: br label [[FLOW10]]
|
||||
; CHECK: Flow10:
|
||||
; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[FLOW8]]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br i1 %b1, label %loop1.header, label %if.else
|
||||
|
||||
if.else:
|
||||
br i1 %b2, label %loop3.latch, label %loop2.header
|
||||
|
||||
loop1.header:
|
||||
br i1 %b3, label %loop1.latch, label %loop1.body
|
||||
|
||||
loop1.latch:
|
||||
br i1 %b4, label %loop1.header, label %exit
|
||||
|
||||
loop1.body:
|
||||
br i1 %b5, label %loop2.header, label %loop1.latch
|
||||
|
||||
loop2.header:
|
||||
br i1 %b6, label %loop2.latch, label %loop2.body
|
||||
|
||||
loop2.body:
|
||||
br i1 %b7, label %loop2.latch, label %loop3.header
|
||||
|
||||
loop2.latch:
|
||||
br i1 %b8, label %loop2.header, label %exit
|
||||
|
||||
loop3.header:
|
||||
br label %loop3.latch
|
||||
|
||||
loop3.latch:
|
||||
br i1 %b9, label %loop3.header, label %exit
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue