diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 5cd7b45c1441..801bcfcaa00b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3065,6 +3065,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, break; case ISD::SMULO: case ISD::UMULO: + case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: if (Op.getResNo() != 1) break; // The boolean result conforms to getBooleanContents. @@ -3519,42 +3520,6 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, Known = KnownBits::smin(Known, Known2); break; } - case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: - if (Op.getResNo() == 1) { - // The boolean result conforms to getBooleanContents. - // If we know the result of a setcc has the top bits zero, use this info. - // We know that we have an integer-based boolean since these operations - // are only available for integer. - if (TLI->getBooleanContents(Op.getValueType().isVector(), false) == - TargetLowering::ZeroOrOneBooleanContent && - BitWidth > 1) - Known.Zero.setBitsFrom(1); - break; - } - LLVM_FALLTHROUGH; - case ISD::ATOMIC_CMP_SWAP: - case ISD::ATOMIC_SWAP: - case ISD::ATOMIC_LOAD_ADD: - case ISD::ATOMIC_LOAD_SUB: - case ISD::ATOMIC_LOAD_AND: - case ISD::ATOMIC_LOAD_CLR: - case ISD::ATOMIC_LOAD_OR: - case ISD::ATOMIC_LOAD_XOR: - case ISD::ATOMIC_LOAD_NAND: - case ISD::ATOMIC_LOAD_MIN: - case ISD::ATOMIC_LOAD_MAX: - case ISD::ATOMIC_LOAD_UMIN: - case ISD::ATOMIC_LOAD_UMAX: - case ISD::ATOMIC_LOAD: { - unsigned MemBits = - cast(Op)->getMemoryVT().getScalarSizeInBits(); - // If we are looking at the loaded value. - if (Op.getResNo() == 0) { - if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND) - Known.Zero.setBitsFrom(MemBits); - } - break; - } case ISD::FrameIndex: case ISD::TargetFrameIndex: TLI->computeKnownBitsForFrameIndex(cast(Op)->getIndex(), @@ -4135,31 +4100,6 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts, assert(Tmp <= VTBits && "Failed to determine minimum sign bits"); return Tmp; } - case ISD::ATOMIC_CMP_SWAP: - case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: - case ISD::ATOMIC_SWAP: - case ISD::ATOMIC_LOAD_ADD: - case ISD::ATOMIC_LOAD_SUB: - case ISD::ATOMIC_LOAD_AND: - case ISD::ATOMIC_LOAD_CLR: - case ISD::ATOMIC_LOAD_OR: - case ISD::ATOMIC_LOAD_XOR: - case ISD::ATOMIC_LOAD_NAND: - case ISD::ATOMIC_LOAD_MIN: - case ISD::ATOMIC_LOAD_MAX: - case ISD::ATOMIC_LOAD_UMIN: - case ISD::ATOMIC_LOAD_UMAX: - case ISD::ATOMIC_LOAD: { - Tmp = cast(Op)->getMemoryVT().getScalarSizeInBits(); - // If we are looking at the loaded value. - if (Op.getResNo() == 0) { - if (TLI->getExtendForAtomicOps() == ISD::SIGN_EXTEND) - return VTBits - Tmp + 1; - if (TLI->getExtendForAtomicOps() == ISD::ZERO_EXTEND) - return VTBits - Tmp; - } - break; - } } // If we are looking at the loaded value of the SDNode. diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td index 1ee6ae196d02..0705437e7569 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td @@ -259,20 +259,26 @@ defm ATOMIC_LOAD32_U_I64 : AtomicLoad; // therefore don't have the extension type field. So instead of matching that, // we match the patterns that the type legalizer expands them to. +// We directly match zext patterns and select the zext atomic loads. +// i32 (zext (i8 (atomic_load_8))) gets legalized to +// i32 (and (i32 (atomic_load_8)), 255) +// These can be selected to a single zero-extending atomic load instruction. +def zext_aload_8_32 : + PatFrag<(ops node:$addr), (and (i32 (atomic_load_8 node:$addr)), 255)>; +def zext_aload_16_32 : + PatFrag<(ops node:$addr), (and (i32 (atomic_load_16 node:$addr)), 65535)>; // Unlike regular loads, extension to i64 is handled differently than i32. // i64 (zext (i8 (atomic_load_8))) gets legalized to // i64 (and (i64 (anyext (i32 (atomic_load_8)))), 255) -// Extension to i32 is elided by SelectionDAG as our atomic loads are -// zero-extending. def zext_aload_8_64 : PatFrag<(ops node:$addr), - (i64 (zext (i32 (atomic_load_8 node:$addr))))>; + (and (i64 (anyext (i32 (atomic_load_8 node:$addr)))), 255)>; def zext_aload_16_64 : PatFrag<(ops node:$addr), - (i64 (zext (i32 (atomic_load_16 node:$addr))))>; + (and (i64 (anyext (i32 (atomic_load_16 node:$addr)))), 65535)>; def zext_aload_32_64 : PatFrag<(ops node:$addr), - (i64 (zext (i32 (atomic_load_32 node:$addr))))>; + (zext (i32 (atomic_load node:$addr)))>; // We don't have single sext atomic load instructions. So for sext loads, we // match bare subword loads (for 32-bit results) and anyext loads (for 64-bit @@ -284,6 +290,8 @@ def sext_aload_16_64 : PatFrag<(ops node:$addr), (anyext (i32 (atomic_load_16 node:$addr)))>; // Select zero-extending loads with no constant offset. +defm : LoadPatNoOffset; +defm : LoadPatNoOffset; defm : LoadPatNoOffset; defm : LoadPatNoOffset; defm : LoadPatNoOffset; @@ -296,6 +304,10 @@ defm : LoadPatNoOffset; // 32->64 sext load gets selected as i32.atomic.load, i64.extend_i32_s // Zero-extending loads with constant offset +defm : LoadPatImmOff; +defm : LoadPatImmOff; +defm : LoadPatImmOff; +defm : LoadPatImmOff; defm : LoadPatImmOff; defm : LoadPatImmOff; defm : LoadPatImmOff; @@ -315,6 +327,8 @@ defm : LoadPatImmOff; // No 32->64 patterns, just use i32.atomic.load and i64.extend_s/i64 // Extending loads with just a constant offset +defm : LoadPatOffsetOnly; +defm : LoadPatOffsetOnly; defm : LoadPatOffsetOnly; defm : LoadPatOffsetOnly; defm : LoadPatOffsetOnly; @@ -323,6 +337,8 @@ defm : LoadPatOffsetOnly; defm : LoadPatOffsetOnly; defm : LoadPatOffsetOnly; +defm : LoadPatGlobalAddrOffOnly; +defm : LoadPatGlobalAddrOffOnly; defm : LoadPatGlobalAddrOffOnly; defm : LoadPatGlobalAddrOffOnly; defm : LoadPatGlobalAddrOffOnly; @@ -635,13 +651,22 @@ defm : BinRMWPattern : - PatFrag<(ops node:$addr, node:$val), (i32 (kind node:$addr, node:$val))>; -class zext_bin_rmw_16_32 : zext_bin_rmw_8_32; + PatFrag<(ops node:$addr, node:$val), + (and (i32 (kind node:$addr, node:$val)), 255)>; +class zext_bin_rmw_16_32 : + PatFrag<(ops node:$addr, node:$val), + (and (i32 (kind node:$addr, node:$val)), 65535)>; class zext_bin_rmw_8_64 : + PatFrag<(ops node:$addr, node:$val), + (and (i64 (anyext (i32 (kind node:$addr, + (i32 (trunc (i64 node:$val))))))), 255)>; +class zext_bin_rmw_16_64 : + PatFrag<(ops node:$addr, node:$val), + (and (i64 (anyext (i32 (kind node:$addr, + (i32 (trunc (i64 node:$val))))))), 65535)>; +class zext_bin_rmw_32_64 : PatFrag<(ops node:$addr, node:$val), (zext (i32 (kind node:$addr, (i32 (trunc (i64 node:$val))))))>; -class zext_bin_rmw_16_64 : zext_bin_rmw_8_64; -class zext_bin_rmw_32_64 : zext_bin_rmw_8_64; // Truncating & sign-extending binary RMW patterns. // These are combined patterns of truncating store patterns and sign-extending @@ -862,8 +887,10 @@ defm : TerRMWPattern : PatFrag<(ops node:$addr, node:$exp, node:$new), - (i32 (kind node:$addr, node:$exp, node:$new))>; -class zext_ter_rmw_16_32 : zext_ter_rmw_8_32; + (and (i32 (kind node:$addr, node:$exp, node:$new)), 255)>; +class zext_ter_rmw_16_32 : + PatFrag<(ops node:$addr, node:$exp, node:$new), + (and (i32 (kind node:$addr, node:$exp, node:$new)), 65535)>; class zext_ter_rmw_8_64 : PatFrag<(ops node:$addr, node:$exp, node:$new), (zext (i32 (assertzext (i32 (kind node:$addr, diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll index c8b67eda156f..c13dea31b1e2 100644 --- a/llvm/test/CodeGen/Mips/atomic.ll +++ b/llvm/test/CodeGen/Mips/atomic.ll @@ -2245,31 +2245,32 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS32-NEXT: addu $1, $2, $25 ; MIPS32-NEXT: lw $1, %got(y)($1) ; MIPS32-NEXT: addiu $2, $zero, -4 -; MIPS32-NEXT: and $3, $1, $2 +; MIPS32-NEXT: and $2, $1, $2 ; MIPS32-NEXT: andi $1, $1, 3 -; MIPS32-NEXT: sll $1, $1, 3 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: sllv $5, $2, $1 +; MIPS32-NEXT: sll $3, $1, 3 +; MIPS32-NEXT: ori $1, $zero, 255 +; MIPS32-NEXT: sllv $5, $1, $3 ; MIPS32-NEXT: nor $6, $zero, $5 -; MIPS32-NEXT: sllv $4, $4, $1 +; MIPS32-NEXT: sllv $4, $4, $3 ; MIPS32-NEXT: $BB8_1: # %entry ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $7, 0($3) +; MIPS32-NEXT: ll $7, 0($2) ; MIPS32-NEXT: addu $8, $7, $4 ; MIPS32-NEXT: and $8, $8, $5 ; MIPS32-NEXT: and $9, $7, $6 ; MIPS32-NEXT: or $9, $9, $8 -; MIPS32-NEXT: sc $9, 0($3) +; MIPS32-NEXT: sc $9, 0($2) ; MIPS32-NEXT: beqz $9, $BB8_1 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $2, $7, $5 -; MIPS32-NEXT: srlv $2, $2, $1 -; MIPS32-NEXT: sll $2, $2, 24 -; MIPS32-NEXT: sra $2, $2, 24 +; MIPS32-NEXT: and $1, $7, $5 +; MIPS32-NEXT: srlv $1, $1, $3 +; MIPS32-NEXT: sll $1, $1, 24 +; MIPS32-NEXT: sra $1, $1, 24 ; MIPS32-NEXT: # %bb.3: # %entry +; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; MIPS32-NEXT: sra $2, $1, 24 ; ; MIPS32O0-LABEL: AtomicLoadAdd8: ; MIPS32O0: # %bb.0: # %entry @@ -2318,30 +2319,30 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS32R2-NEXT: addu $1, $2, $25 ; MIPS32R2-NEXT: lw $1, %got(y)($1) ; MIPS32R2-NEXT: addiu $2, $zero, -4 -; MIPS32R2-NEXT: and $3, $1, $2 +; MIPS32R2-NEXT: and $2, $1, $2 ; MIPS32R2-NEXT: andi $1, $1, 3 -; MIPS32R2-NEXT: sll $1, $1, 3 -; MIPS32R2-NEXT: ori $2, $zero, 255 -; MIPS32R2-NEXT: sllv $5, $2, $1 +; MIPS32R2-NEXT: sll $3, $1, 3 +; MIPS32R2-NEXT: ori $1, $zero, 255 +; MIPS32R2-NEXT: sllv $5, $1, $3 ; MIPS32R2-NEXT: nor $6, $zero, $5 -; MIPS32R2-NEXT: sllv $4, $4, $1 +; MIPS32R2-NEXT: sllv $4, $4, $3 ; MIPS32R2-NEXT: $BB8_1: # %entry ; MIPS32R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R2-NEXT: ll $7, 0($3) +; MIPS32R2-NEXT: ll $7, 0($2) ; MIPS32R2-NEXT: addu $8, $7, $4 ; MIPS32R2-NEXT: and $8, $8, $5 ; MIPS32R2-NEXT: and $9, $7, $6 ; MIPS32R2-NEXT: or $9, $9, $8 -; MIPS32R2-NEXT: sc $9, 0($3) +; MIPS32R2-NEXT: sc $9, 0($2) ; MIPS32R2-NEXT: beqz $9, $BB8_1 ; MIPS32R2-NEXT: nop ; MIPS32R2-NEXT: # %bb.2: # %entry -; MIPS32R2-NEXT: and $2, $7, $5 -; MIPS32R2-NEXT: srlv $2, $2, $1 -; MIPS32R2-NEXT: seb $2, $2 +; MIPS32R2-NEXT: and $1, $7, $5 +; MIPS32R2-NEXT: srlv $1, $1, $3 +; MIPS32R2-NEXT: seb $1, $1 ; MIPS32R2-NEXT: # %bb.3: # %entry ; MIPS32R2-NEXT: jr $ra -; MIPS32R2-NEXT: nop +; MIPS32R2-NEXT: seb $2, $1 ; ; MIPS32R6-LABEL: AtomicLoadAdd8: ; MIPS32R6: # %bb.0: # %entry @@ -2350,28 +2351,29 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS32R6-NEXT: addu $1, $2, $25 ; MIPS32R6-NEXT: lw $1, %got(y)($1) ; MIPS32R6-NEXT: addiu $2, $zero, -4 -; MIPS32R6-NEXT: and $3, $1, $2 +; MIPS32R6-NEXT: and $2, $1, $2 ; MIPS32R6-NEXT: andi $1, $1, 3 -; MIPS32R6-NEXT: sll $1, $1, 3 -; MIPS32R6-NEXT: ori $2, $zero, 255 -; MIPS32R6-NEXT: sllv $5, $2, $1 +; MIPS32R6-NEXT: sll $3, $1, 3 +; MIPS32R6-NEXT: ori $1, $zero, 255 +; MIPS32R6-NEXT: sllv $5, $1, $3 ; MIPS32R6-NEXT: nor $6, $zero, $5 -; MIPS32R6-NEXT: sllv $4, $4, $1 +; MIPS32R6-NEXT: sllv $4, $4, $3 ; MIPS32R6-NEXT: $BB8_1: # %entry ; MIPS32R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R6-NEXT: ll $7, 0($3) +; MIPS32R6-NEXT: ll $7, 0($2) ; MIPS32R6-NEXT: addu $8, $7, $4 ; MIPS32R6-NEXT: and $8, $8, $5 ; MIPS32R6-NEXT: and $9, $7, $6 ; MIPS32R6-NEXT: or $9, $9, $8 -; MIPS32R6-NEXT: sc $9, 0($3) +; MIPS32R6-NEXT: sc $9, 0($2) ; MIPS32R6-NEXT: beqzc $9, $BB8_1 ; MIPS32R6-NEXT: # %bb.2: # %entry -; MIPS32R6-NEXT: and $2, $7, $5 -; MIPS32R6-NEXT: srlv $2, $2, $1 -; MIPS32R6-NEXT: seb $2, $2 +; MIPS32R6-NEXT: and $1, $7, $5 +; MIPS32R6-NEXT: srlv $1, $1, $3 +; MIPS32R6-NEXT: seb $1, $1 ; MIPS32R6-NEXT: # %bb.3: # %entry -; MIPS32R6-NEXT: jrc $ra +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seb $2, $1 ; ; MIPS32R6O0-LABEL: AtomicLoadAdd8: ; MIPS32R6O0: # %bb.0: # %entry @@ -2405,7 +2407,8 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS32R6O0-NEXT: # %bb.3: # %entry ; MIPS32R6O0-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS32R6O0-NEXT: # %bb.4: # %entry -; MIPS32R6O0-NEXT: lw $2, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: lw $1, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: seb $2, $1 ; MIPS32R6O0-NEXT: addiu $sp, $sp, 8 ; MIPS32R6O0-NEXT: jrc $ra ; @@ -2416,31 +2419,32 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS4-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8))) ; MIPS4-NEXT: ld $1, %got_disp(y)($1) ; MIPS4-NEXT: daddiu $2, $zero, -4 -; MIPS4-NEXT: and $3, $1, $2 +; MIPS4-NEXT: and $2, $1, $2 ; MIPS4-NEXT: andi $1, $1, 3 -; MIPS4-NEXT: sll $1, $1, 3 -; MIPS4-NEXT: ori $2, $zero, 255 -; MIPS4-NEXT: sllv $5, $2, $1 +; MIPS4-NEXT: sll $3, $1, 3 +; MIPS4-NEXT: ori $1, $zero, 255 +; MIPS4-NEXT: sllv $5, $1, $3 ; MIPS4-NEXT: nor $6, $zero, $5 -; MIPS4-NEXT: sllv $4, $4, $1 +; MIPS4-NEXT: sllv $4, $4, $3 ; MIPS4-NEXT: .LBB8_1: # %entry ; MIPS4-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS4-NEXT: ll $7, 0($3) +; MIPS4-NEXT: ll $7, 0($2) ; MIPS4-NEXT: addu $8, $7, $4 ; MIPS4-NEXT: and $8, $8, $5 ; MIPS4-NEXT: and $9, $7, $6 ; MIPS4-NEXT: or $9, $9, $8 -; MIPS4-NEXT: sc $9, 0($3) +; MIPS4-NEXT: sc $9, 0($2) ; MIPS4-NEXT: beqz $9, .LBB8_1 ; MIPS4-NEXT: nop ; MIPS4-NEXT: # %bb.2: # %entry -; MIPS4-NEXT: and $2, $7, $5 -; MIPS4-NEXT: srlv $2, $2, $1 -; MIPS4-NEXT: sll $2, $2, 24 -; MIPS4-NEXT: sra $2, $2, 24 +; MIPS4-NEXT: and $1, $7, $5 +; MIPS4-NEXT: srlv $1, $1, $3 +; MIPS4-NEXT: sll $1, $1, 24 +; MIPS4-NEXT: sra $1, $1, 24 ; MIPS4-NEXT: # %bb.3: # %entry +; MIPS4-NEXT: sll $1, $1, 24 ; MIPS4-NEXT: jr $ra -; MIPS4-NEXT: nop +; MIPS4-NEXT: sra $2, $1, 24 ; ; MIPS64-LABEL: AtomicLoadAdd8: ; MIPS64: # %bb.0: # %entry @@ -2449,31 +2453,32 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8))) ; MIPS64-NEXT: ld $1, %got_disp(y)($1) ; MIPS64-NEXT: daddiu $2, $zero, -4 -; MIPS64-NEXT: and $3, $1, $2 +; MIPS64-NEXT: and $2, $1, $2 ; MIPS64-NEXT: andi $1, $1, 3 -; MIPS64-NEXT: sll $1, $1, 3 -; MIPS64-NEXT: ori $2, $zero, 255 -; MIPS64-NEXT: sllv $5, $2, $1 +; MIPS64-NEXT: sll $3, $1, 3 +; MIPS64-NEXT: ori $1, $zero, 255 +; MIPS64-NEXT: sllv $5, $1, $3 ; MIPS64-NEXT: nor $6, $zero, $5 -; MIPS64-NEXT: sllv $4, $4, $1 +; MIPS64-NEXT: sllv $4, $4, $3 ; MIPS64-NEXT: .LBB8_1: # %entry ; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64-NEXT: ll $7, 0($3) +; MIPS64-NEXT: ll $7, 0($2) ; MIPS64-NEXT: addu $8, $7, $4 ; MIPS64-NEXT: and $8, $8, $5 ; MIPS64-NEXT: and $9, $7, $6 ; MIPS64-NEXT: or $9, $9, $8 -; MIPS64-NEXT: sc $9, 0($3) +; MIPS64-NEXT: sc $9, 0($2) ; MIPS64-NEXT: beqz $9, .LBB8_1 ; MIPS64-NEXT: nop ; MIPS64-NEXT: # %bb.2: # %entry -; MIPS64-NEXT: and $2, $7, $5 -; MIPS64-NEXT: srlv $2, $2, $1 -; MIPS64-NEXT: sll $2, $2, 24 -; MIPS64-NEXT: sra $2, $2, 24 +; MIPS64-NEXT: and $1, $7, $5 +; MIPS64-NEXT: srlv $1, $1, $3 +; MIPS64-NEXT: sll $1, $1, 24 +; MIPS64-NEXT: sra $1, $1, 24 ; MIPS64-NEXT: # %bb.3: # %entry +; MIPS64-NEXT: sll $1, $1, 24 ; MIPS64-NEXT: jr $ra -; MIPS64-NEXT: nop +; MIPS64-NEXT: sra $2, $1, 24 ; ; MIPS64R2-LABEL: AtomicLoadAdd8: ; MIPS64R2: # %bb.0: # %entry @@ -2482,30 +2487,30 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8))) ; MIPS64R2-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R2-NEXT: daddiu $2, $zero, -4 -; MIPS64R2-NEXT: and $3, $1, $2 +; MIPS64R2-NEXT: and $2, $1, $2 ; MIPS64R2-NEXT: andi $1, $1, 3 -; MIPS64R2-NEXT: sll $1, $1, 3 -; MIPS64R2-NEXT: ori $2, $zero, 255 -; MIPS64R2-NEXT: sllv $5, $2, $1 +; MIPS64R2-NEXT: sll $3, $1, 3 +; MIPS64R2-NEXT: ori $1, $zero, 255 +; MIPS64R2-NEXT: sllv $5, $1, $3 ; MIPS64R2-NEXT: nor $6, $zero, $5 -; MIPS64R2-NEXT: sllv $4, $4, $1 +; MIPS64R2-NEXT: sllv $4, $4, $3 ; MIPS64R2-NEXT: .LBB8_1: # %entry ; MIPS64R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R2-NEXT: ll $7, 0($3) +; MIPS64R2-NEXT: ll $7, 0($2) ; MIPS64R2-NEXT: addu $8, $7, $4 ; MIPS64R2-NEXT: and $8, $8, $5 ; MIPS64R2-NEXT: and $9, $7, $6 ; MIPS64R2-NEXT: or $9, $9, $8 -; MIPS64R2-NEXT: sc $9, 0($3) +; MIPS64R2-NEXT: sc $9, 0($2) ; MIPS64R2-NEXT: beqz $9, .LBB8_1 ; MIPS64R2-NEXT: nop ; MIPS64R2-NEXT: # %bb.2: # %entry -; MIPS64R2-NEXT: and $2, $7, $5 -; MIPS64R2-NEXT: srlv $2, $2, $1 -; MIPS64R2-NEXT: seb $2, $2 +; MIPS64R2-NEXT: and $1, $7, $5 +; MIPS64R2-NEXT: srlv $1, $1, $3 +; MIPS64R2-NEXT: seb $1, $1 ; MIPS64R2-NEXT: # %bb.3: # %entry ; MIPS64R2-NEXT: jr $ra -; MIPS64R2-NEXT: nop +; MIPS64R2-NEXT: seb $2, $1 ; ; MIPS64R6-LABEL: AtomicLoadAdd8: ; MIPS64R6: # %bb.0: # %entry @@ -2514,28 +2519,29 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd8))) ; MIPS64R6-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R6-NEXT: daddiu $2, $zero, -4 -; MIPS64R6-NEXT: and $3, $1, $2 +; MIPS64R6-NEXT: and $2, $1, $2 ; MIPS64R6-NEXT: andi $1, $1, 3 -; MIPS64R6-NEXT: sll $1, $1, 3 -; MIPS64R6-NEXT: ori $2, $zero, 255 -; MIPS64R6-NEXT: sllv $5, $2, $1 +; MIPS64R6-NEXT: sll $3, $1, 3 +; MIPS64R6-NEXT: ori $1, $zero, 255 +; MIPS64R6-NEXT: sllv $5, $1, $3 ; MIPS64R6-NEXT: nor $6, $zero, $5 -; MIPS64R6-NEXT: sllv $4, $4, $1 +; MIPS64R6-NEXT: sllv $4, $4, $3 ; MIPS64R6-NEXT: .LBB8_1: # %entry ; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R6-NEXT: ll $7, 0($3) +; MIPS64R6-NEXT: ll $7, 0($2) ; MIPS64R6-NEXT: addu $8, $7, $4 ; MIPS64R6-NEXT: and $8, $8, $5 ; MIPS64R6-NEXT: and $9, $7, $6 ; MIPS64R6-NEXT: or $9, $9, $8 -; MIPS64R6-NEXT: sc $9, 0($3) +; MIPS64R6-NEXT: sc $9, 0($2) ; MIPS64R6-NEXT: beqzc $9, .LBB8_1 ; MIPS64R6-NEXT: # %bb.2: # %entry -; MIPS64R6-NEXT: and $2, $7, $5 -; MIPS64R6-NEXT: srlv $2, $2, $1 -; MIPS64R6-NEXT: seb $2, $2 +; MIPS64R6-NEXT: and $1, $7, $5 +; MIPS64R6-NEXT: srlv $1, $1, $3 +; MIPS64R6-NEXT: seb $1, $1 ; MIPS64R6-NEXT: # %bb.3: # %entry -; MIPS64R6-NEXT: jrc $ra +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seb $2, $1 ; ; MIPS64R6O0-LABEL: AtomicLoadAdd8: ; MIPS64R6O0: # %bb.0: # %entry @@ -2570,7 +2576,8 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS64R6O0-NEXT: # %bb.3: # %entry ; MIPS64R6O0-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64R6O0-NEXT: # %bb.4: # %entry -; MIPS64R6O0-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: lw $1, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: seb $2, $1 ; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16 ; MIPS64R6O0-NEXT: jrc $ra ; @@ -2581,28 +2588,29 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MM32-NEXT: addu $2, $2, $25 ; MM32-NEXT: lw $1, %got(y)($2) ; MM32-NEXT: addiu $2, $zero, -4 -; MM32-NEXT: and $3, $1, $2 +; MM32-NEXT: and $2, $1, $2 ; MM32-NEXT: andi $1, $1, 3 -; MM32-NEXT: sll $1, $1, 3 -; MM32-NEXT: ori $2, $zero, 255 -; MM32-NEXT: sllv $5, $2, $1 +; MM32-NEXT: sll $3, $1, 3 +; MM32-NEXT: ori $1, $zero, 255 +; MM32-NEXT: sllv $5, $1, $3 ; MM32-NEXT: nor $6, $zero, $5 -; MM32-NEXT: sllv $4, $4, $1 +; MM32-NEXT: sllv $4, $4, $3 ; MM32-NEXT: $BB8_1: # %entry ; MM32-NEXT: # =>This Inner Loop Header: Depth=1 -; MM32-NEXT: ll $7, 0($3) +; MM32-NEXT: ll $7, 0($2) ; MM32-NEXT: addu $8, $7, $4 ; MM32-NEXT: and $8, $8, $5 ; MM32-NEXT: and $9, $7, $6 ; MM32-NEXT: or $9, $9, $8 -; MM32-NEXT: sc $9, 0($3) +; MM32-NEXT: sc $9, 0($2) ; MM32-NEXT: beqzc $9, $BB8_1 ; MM32-NEXT: # %bb.2: # %entry -; MM32-NEXT: and $2, $7, $5 -; MM32-NEXT: srlv $2, $2, $1 -; MM32-NEXT: seb $2, $2 +; MM32-NEXT: and $1, $7, $5 +; MM32-NEXT: srlv $1, $1, $3 +; MM32-NEXT: seb $1, $1 ; MM32-NEXT: # %bb.3: # %entry -; MM32-NEXT: jrc $ra +; MM32-NEXT: jr $ra +; MM32-NEXT: seb $2, $1 ; ; O1-LABEL: AtomicLoadAdd8: ; O1: # %bb.0: # %entry @@ -2611,31 +2619,32 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; O1-NEXT: addu $1, $2, $25 ; O1-NEXT: lw $1, %got(y)($1) ; O1-NEXT: addiu $2, $zero, -4 -; O1-NEXT: and $3, $1, $2 +; O1-NEXT: and $2, $1, $2 ; O1-NEXT: andi $1, $1, 3 -; O1-NEXT: sll $1, $1, 3 -; O1-NEXT: ori $2, $zero, 255 -; O1-NEXT: sllv $5, $2, $1 +; O1-NEXT: sll $3, $1, 3 +; O1-NEXT: ori $1, $zero, 255 +; O1-NEXT: sllv $5, $1, $3 ; O1-NEXT: nor $6, $zero, $5 -; O1-NEXT: sllv $4, $4, $1 +; O1-NEXT: sllv $4, $4, $3 ; O1-NEXT: $BB8_1: # %entry ; O1-NEXT: # =>This Inner Loop Header: Depth=1 -; O1-NEXT: ll $7, 0($3) +; O1-NEXT: ll $7, 0($2) ; O1-NEXT: addu $8, $7, $4 ; O1-NEXT: and $8, $8, $5 ; O1-NEXT: and $9, $7, $6 ; O1-NEXT: or $9, $9, $8 -; O1-NEXT: sc $9, 0($3) +; O1-NEXT: sc $9, 0($2) ; O1-NEXT: beqz $9, $BB8_1 ; O1-NEXT: nop ; O1-NEXT: # %bb.2: # %entry -; O1-NEXT: and $2, $7, $5 -; O1-NEXT: srlv $2, $2, $1 -; O1-NEXT: sll $2, $2, 24 -; O1-NEXT: sra $2, $2, 24 +; O1-NEXT: and $1, $7, $5 +; O1-NEXT: srlv $1, $1, $3 +; O1-NEXT: sll $1, $1, 24 +; O1-NEXT: sra $1, $1, 24 ; O1-NEXT: # %bb.3: # %entry +; O1-NEXT: sll $1, $1, 24 ; O1-NEXT: jr $ra -; O1-NEXT: nop +; O1-NEXT: sra $2, $1, 24 ; ; O2-LABEL: AtomicLoadAdd8: ; O2: # %bb.0: # %entry @@ -2644,31 +2653,32 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; O2-NEXT: addu $1, $2, $25 ; O2-NEXT: lw $1, %got(y)($1) ; O2-NEXT: addiu $2, $zero, -4 -; O2-NEXT: and $3, $1, $2 +; O2-NEXT: and $2, $1, $2 ; O2-NEXT: andi $1, $1, 3 -; O2-NEXT: sll $1, $1, 3 -; O2-NEXT: ori $2, $zero, 255 -; O2-NEXT: sllv $5, $2, $1 +; O2-NEXT: sll $3, $1, 3 +; O2-NEXT: ori $1, $zero, 255 +; O2-NEXT: sllv $5, $1, $3 ; O2-NEXT: nor $6, $zero, $5 -; O2-NEXT: sllv $4, $4, $1 +; O2-NEXT: sllv $4, $4, $3 ; O2-NEXT: $BB8_1: # %entry ; O2-NEXT: # =>This Inner Loop Header: Depth=1 -; O2-NEXT: ll $7, 0($3) +; O2-NEXT: ll $7, 0($2) ; O2-NEXT: addu $8, $7, $4 ; O2-NEXT: and $8, $8, $5 ; O2-NEXT: and $9, $7, $6 ; O2-NEXT: or $9, $9, $8 -; O2-NEXT: sc $9, 0($3) +; O2-NEXT: sc $9, 0($2) ; O2-NEXT: beqz $9, $BB8_1 ; O2-NEXT: nop ; O2-NEXT: # %bb.2: # %entry -; O2-NEXT: and $2, $7, $5 -; O2-NEXT: srlv $2, $2, $1 -; O2-NEXT: sll $2, $2, 24 -; O2-NEXT: sra $2, $2, 24 +; O2-NEXT: and $1, $7, $5 +; O2-NEXT: srlv $1, $1, $3 +; O2-NEXT: sll $1, $1, 24 +; O2-NEXT: sra $1, $1, 24 ; O2-NEXT: # %bb.3: # %entry +; O2-NEXT: sll $1, $1, 24 ; O2-NEXT: jr $ra -; O2-NEXT: nop +; O2-NEXT: sra $2, $1, 24 ; ; O3-LABEL: AtomicLoadAdd8: ; O3: # %bb.0: # %entry @@ -2677,31 +2687,32 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; O3-NEXT: addu $1, $2, $25 ; O3-NEXT: addiu $2, $zero, -4 ; O3-NEXT: lw $1, %got(y)($1) -; O3-NEXT: and $3, $1, $2 +; O3-NEXT: and $2, $1, $2 ; O3-NEXT: andi $1, $1, 3 -; O3-NEXT: ori $2, $zero, 255 -; O3-NEXT: sll $1, $1, 3 -; O3-NEXT: sllv $5, $2, $1 -; O3-NEXT: sllv $4, $4, $1 +; O3-NEXT: sll $3, $1, 3 +; O3-NEXT: ori $1, $zero, 255 +; O3-NEXT: sllv $5, $1, $3 +; O3-NEXT: sllv $4, $4, $3 ; O3-NEXT: nor $6, $zero, $5 ; O3-NEXT: $BB8_1: # %entry ; O3-NEXT: # =>This Inner Loop Header: Depth=1 -; O3-NEXT: ll $7, 0($3) +; O3-NEXT: ll $7, 0($2) ; O3-NEXT: addu $8, $7, $4 ; O3-NEXT: and $8, $8, $5 ; O3-NEXT: and $9, $7, $6 ; O3-NEXT: or $9, $9, $8 -; O3-NEXT: sc $9, 0($3) +; O3-NEXT: sc $9, 0($2) ; O3-NEXT: beqz $9, $BB8_1 ; O3-NEXT: nop ; O3-NEXT: # %bb.2: # %entry -; O3-NEXT: and $2, $7, $5 -; O3-NEXT: srlv $2, $2, $1 -; O3-NEXT: sll $2, $2, 24 -; O3-NEXT: sra $2, $2, 24 +; O3-NEXT: and $1, $7, $5 +; O3-NEXT: srlv $1, $1, $3 +; O3-NEXT: sll $1, $1, 24 +; O3-NEXT: sra $1, $1, 24 ; O3-NEXT: # %bb.3: # %entry +; O3-NEXT: sll $1, $1, 24 ; O3-NEXT: jr $ra -; O3-NEXT: nop +; O3-NEXT: sra $2, $1, 24 ; ; MIPS32EB-LABEL: AtomicLoadAdd8: ; MIPS32EB: # %bb.0: # %entry @@ -2710,32 +2721,33 @@ define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { ; MIPS32EB-NEXT: addu $1, $2, $25 ; MIPS32EB-NEXT: lw $1, %got(y)($1) ; MIPS32EB-NEXT: addiu $2, $zero, -4 -; MIPS32EB-NEXT: and $3, $1, $2 +; MIPS32EB-NEXT: and $2, $1, $2 ; MIPS32EB-NEXT: andi $1, $1, 3 ; MIPS32EB-NEXT: xori $1, $1, 3 -; MIPS32EB-NEXT: sll $1, $1, 3 -; MIPS32EB-NEXT: ori $2, $zero, 255 -; MIPS32EB-NEXT: sllv $5, $2, $1 +; MIPS32EB-NEXT: sll $3, $1, 3 +; MIPS32EB-NEXT: ori $1, $zero, 255 +; MIPS32EB-NEXT: sllv $5, $1, $3 ; MIPS32EB-NEXT: nor $6, $zero, $5 -; MIPS32EB-NEXT: sllv $4, $4, $1 +; MIPS32EB-NEXT: sllv $4, $4, $3 ; MIPS32EB-NEXT: $BB8_1: # %entry ; MIPS32EB-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32EB-NEXT: ll $7, 0($3) +; MIPS32EB-NEXT: ll $7, 0($2) ; MIPS32EB-NEXT: addu $8, $7, $4 ; MIPS32EB-NEXT: and $8, $8, $5 ; MIPS32EB-NEXT: and $9, $7, $6 ; MIPS32EB-NEXT: or $9, $9, $8 -; MIPS32EB-NEXT: sc $9, 0($3) +; MIPS32EB-NEXT: sc $9, 0($2) ; MIPS32EB-NEXT: beqz $9, $BB8_1 ; MIPS32EB-NEXT: nop ; MIPS32EB-NEXT: # %bb.2: # %entry -; MIPS32EB-NEXT: and $2, $7, $5 -; MIPS32EB-NEXT: srlv $2, $2, $1 -; MIPS32EB-NEXT: sll $2, $2, 24 -; MIPS32EB-NEXT: sra $2, $2, 24 +; MIPS32EB-NEXT: and $1, $7, $5 +; MIPS32EB-NEXT: srlv $1, $1, $3 +; MIPS32EB-NEXT: sll $1, $1, 24 +; MIPS32EB-NEXT: sra $1, $1, 24 ; MIPS32EB-NEXT: # %bb.3: # %entry +; MIPS32EB-NEXT: sll $1, $1, 24 ; MIPS32EB-NEXT: jr $ra -; MIPS32EB-NEXT: nop +; MIPS32EB-NEXT: sra $2, $1, 24 entry: %0 = atomicrmw add i8* @y, i8 %incr monotonic ret i8 %0 @@ -2749,31 +2761,32 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS32-NEXT: addu $1, $2, $25 ; MIPS32-NEXT: lw $1, %got(y)($1) ; MIPS32-NEXT: addiu $2, $zero, -4 -; MIPS32-NEXT: and $3, $1, $2 +; MIPS32-NEXT: and $2, $1, $2 ; MIPS32-NEXT: andi $1, $1, 3 -; MIPS32-NEXT: sll $1, $1, 3 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: sllv $5, $2, $1 +; MIPS32-NEXT: sll $3, $1, 3 +; MIPS32-NEXT: ori $1, $zero, 255 +; MIPS32-NEXT: sllv $5, $1, $3 ; MIPS32-NEXT: nor $6, $zero, $5 -; MIPS32-NEXT: sllv $4, $4, $1 +; MIPS32-NEXT: sllv $4, $4, $3 ; MIPS32-NEXT: $BB9_1: # %entry ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $7, 0($3) +; MIPS32-NEXT: ll $7, 0($2) ; MIPS32-NEXT: subu $8, $7, $4 ; MIPS32-NEXT: and $8, $8, $5 ; MIPS32-NEXT: and $9, $7, $6 ; MIPS32-NEXT: or $9, $9, $8 -; MIPS32-NEXT: sc $9, 0($3) +; MIPS32-NEXT: sc $9, 0($2) ; MIPS32-NEXT: beqz $9, $BB9_1 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $2, $7, $5 -; MIPS32-NEXT: srlv $2, $2, $1 -; MIPS32-NEXT: sll $2, $2, 24 -; MIPS32-NEXT: sra $2, $2, 24 +; MIPS32-NEXT: and $1, $7, $5 +; MIPS32-NEXT: srlv $1, $1, $3 +; MIPS32-NEXT: sll $1, $1, 24 +; MIPS32-NEXT: sra $1, $1, 24 ; MIPS32-NEXT: # %bb.3: # %entry +; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; MIPS32-NEXT: sra $2, $1, 24 ; ; MIPS32O0-LABEL: AtomicLoadSub8: ; MIPS32O0: # %bb.0: # %entry @@ -2822,30 +2835,30 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS32R2-NEXT: addu $1, $2, $25 ; MIPS32R2-NEXT: lw $1, %got(y)($1) ; MIPS32R2-NEXT: addiu $2, $zero, -4 -; MIPS32R2-NEXT: and $3, $1, $2 +; MIPS32R2-NEXT: and $2, $1, $2 ; MIPS32R2-NEXT: andi $1, $1, 3 -; MIPS32R2-NEXT: sll $1, $1, 3 -; MIPS32R2-NEXT: ori $2, $zero, 255 -; MIPS32R2-NEXT: sllv $5, $2, $1 +; MIPS32R2-NEXT: sll $3, $1, 3 +; MIPS32R2-NEXT: ori $1, $zero, 255 +; MIPS32R2-NEXT: sllv $5, $1, $3 ; MIPS32R2-NEXT: nor $6, $zero, $5 -; MIPS32R2-NEXT: sllv $4, $4, $1 +; MIPS32R2-NEXT: sllv $4, $4, $3 ; MIPS32R2-NEXT: $BB9_1: # %entry ; MIPS32R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R2-NEXT: ll $7, 0($3) +; MIPS32R2-NEXT: ll $7, 0($2) ; MIPS32R2-NEXT: subu $8, $7, $4 ; MIPS32R2-NEXT: and $8, $8, $5 ; MIPS32R2-NEXT: and $9, $7, $6 ; MIPS32R2-NEXT: or $9, $9, $8 -; MIPS32R2-NEXT: sc $9, 0($3) +; MIPS32R2-NEXT: sc $9, 0($2) ; MIPS32R2-NEXT: beqz $9, $BB9_1 ; MIPS32R2-NEXT: nop ; MIPS32R2-NEXT: # %bb.2: # %entry -; MIPS32R2-NEXT: and $2, $7, $5 -; MIPS32R2-NEXT: srlv $2, $2, $1 -; MIPS32R2-NEXT: seb $2, $2 +; MIPS32R2-NEXT: and $1, $7, $5 +; MIPS32R2-NEXT: srlv $1, $1, $3 +; MIPS32R2-NEXT: seb $1, $1 ; MIPS32R2-NEXT: # %bb.3: # %entry ; MIPS32R2-NEXT: jr $ra -; MIPS32R2-NEXT: nop +; MIPS32R2-NEXT: seb $2, $1 ; ; MIPS32R6-LABEL: AtomicLoadSub8: ; MIPS32R6: # %bb.0: # %entry @@ -2854,28 +2867,29 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS32R6-NEXT: addu $1, $2, $25 ; MIPS32R6-NEXT: lw $1, %got(y)($1) ; MIPS32R6-NEXT: addiu $2, $zero, -4 -; MIPS32R6-NEXT: and $3, $1, $2 +; MIPS32R6-NEXT: and $2, $1, $2 ; MIPS32R6-NEXT: andi $1, $1, 3 -; MIPS32R6-NEXT: sll $1, $1, 3 -; MIPS32R6-NEXT: ori $2, $zero, 255 -; MIPS32R6-NEXT: sllv $5, $2, $1 +; MIPS32R6-NEXT: sll $3, $1, 3 +; MIPS32R6-NEXT: ori $1, $zero, 255 +; MIPS32R6-NEXT: sllv $5, $1, $3 ; MIPS32R6-NEXT: nor $6, $zero, $5 -; MIPS32R6-NEXT: sllv $4, $4, $1 +; MIPS32R6-NEXT: sllv $4, $4, $3 ; MIPS32R6-NEXT: $BB9_1: # %entry ; MIPS32R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R6-NEXT: ll $7, 0($3) +; MIPS32R6-NEXT: ll $7, 0($2) ; MIPS32R6-NEXT: subu $8, $7, $4 ; MIPS32R6-NEXT: and $8, $8, $5 ; MIPS32R6-NEXT: and $9, $7, $6 ; MIPS32R6-NEXT: or $9, $9, $8 -; MIPS32R6-NEXT: sc $9, 0($3) +; MIPS32R6-NEXT: sc $9, 0($2) ; MIPS32R6-NEXT: beqzc $9, $BB9_1 ; MIPS32R6-NEXT: # %bb.2: # %entry -; MIPS32R6-NEXT: and $2, $7, $5 -; MIPS32R6-NEXT: srlv $2, $2, $1 -; MIPS32R6-NEXT: seb $2, $2 +; MIPS32R6-NEXT: and $1, $7, $5 +; MIPS32R6-NEXT: srlv $1, $1, $3 +; MIPS32R6-NEXT: seb $1, $1 ; MIPS32R6-NEXT: # %bb.3: # %entry -; MIPS32R6-NEXT: jrc $ra +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seb $2, $1 ; ; MIPS32R6O0-LABEL: AtomicLoadSub8: ; MIPS32R6O0: # %bb.0: # %entry @@ -2909,7 +2923,8 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS32R6O0-NEXT: # %bb.3: # %entry ; MIPS32R6O0-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS32R6O0-NEXT: # %bb.4: # %entry -; MIPS32R6O0-NEXT: lw $2, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: lw $1, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: seb $2, $1 ; MIPS32R6O0-NEXT: addiu $sp, $sp, 8 ; MIPS32R6O0-NEXT: jrc $ra ; @@ -2920,31 +2935,32 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS4-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8))) ; MIPS4-NEXT: ld $1, %got_disp(y)($1) ; MIPS4-NEXT: daddiu $2, $zero, -4 -; MIPS4-NEXT: and $3, $1, $2 +; MIPS4-NEXT: and $2, $1, $2 ; MIPS4-NEXT: andi $1, $1, 3 -; MIPS4-NEXT: sll $1, $1, 3 -; MIPS4-NEXT: ori $2, $zero, 255 -; MIPS4-NEXT: sllv $5, $2, $1 +; MIPS4-NEXT: sll $3, $1, 3 +; MIPS4-NEXT: ori $1, $zero, 255 +; MIPS4-NEXT: sllv $5, $1, $3 ; MIPS4-NEXT: nor $6, $zero, $5 -; MIPS4-NEXT: sllv $4, $4, $1 +; MIPS4-NEXT: sllv $4, $4, $3 ; MIPS4-NEXT: .LBB9_1: # %entry ; MIPS4-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS4-NEXT: ll $7, 0($3) +; MIPS4-NEXT: ll $7, 0($2) ; MIPS4-NEXT: subu $8, $7, $4 ; MIPS4-NEXT: and $8, $8, $5 ; MIPS4-NEXT: and $9, $7, $6 ; MIPS4-NEXT: or $9, $9, $8 -; MIPS4-NEXT: sc $9, 0($3) +; MIPS4-NEXT: sc $9, 0($2) ; MIPS4-NEXT: beqz $9, .LBB9_1 ; MIPS4-NEXT: nop ; MIPS4-NEXT: # %bb.2: # %entry -; MIPS4-NEXT: and $2, $7, $5 -; MIPS4-NEXT: srlv $2, $2, $1 -; MIPS4-NEXT: sll $2, $2, 24 -; MIPS4-NEXT: sra $2, $2, 24 +; MIPS4-NEXT: and $1, $7, $5 +; MIPS4-NEXT: srlv $1, $1, $3 +; MIPS4-NEXT: sll $1, $1, 24 +; MIPS4-NEXT: sra $1, $1, 24 ; MIPS4-NEXT: # %bb.3: # %entry +; MIPS4-NEXT: sll $1, $1, 24 ; MIPS4-NEXT: jr $ra -; MIPS4-NEXT: nop +; MIPS4-NEXT: sra $2, $1, 24 ; ; MIPS64-LABEL: AtomicLoadSub8: ; MIPS64: # %bb.0: # %entry @@ -2953,31 +2969,32 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8))) ; MIPS64-NEXT: ld $1, %got_disp(y)($1) ; MIPS64-NEXT: daddiu $2, $zero, -4 -; MIPS64-NEXT: and $3, $1, $2 +; MIPS64-NEXT: and $2, $1, $2 ; MIPS64-NEXT: andi $1, $1, 3 -; MIPS64-NEXT: sll $1, $1, 3 -; MIPS64-NEXT: ori $2, $zero, 255 -; MIPS64-NEXT: sllv $5, $2, $1 +; MIPS64-NEXT: sll $3, $1, 3 +; MIPS64-NEXT: ori $1, $zero, 255 +; MIPS64-NEXT: sllv $5, $1, $3 ; MIPS64-NEXT: nor $6, $zero, $5 -; MIPS64-NEXT: sllv $4, $4, $1 +; MIPS64-NEXT: sllv $4, $4, $3 ; MIPS64-NEXT: .LBB9_1: # %entry ; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64-NEXT: ll $7, 0($3) +; MIPS64-NEXT: ll $7, 0($2) ; MIPS64-NEXT: subu $8, $7, $4 ; MIPS64-NEXT: and $8, $8, $5 ; MIPS64-NEXT: and $9, $7, $6 ; MIPS64-NEXT: or $9, $9, $8 -; MIPS64-NEXT: sc $9, 0($3) +; MIPS64-NEXT: sc $9, 0($2) ; MIPS64-NEXT: beqz $9, .LBB9_1 ; MIPS64-NEXT: nop ; MIPS64-NEXT: # %bb.2: # %entry -; MIPS64-NEXT: and $2, $7, $5 -; MIPS64-NEXT: srlv $2, $2, $1 -; MIPS64-NEXT: sll $2, $2, 24 -; MIPS64-NEXT: sra $2, $2, 24 +; MIPS64-NEXT: and $1, $7, $5 +; MIPS64-NEXT: srlv $1, $1, $3 +; MIPS64-NEXT: sll $1, $1, 24 +; MIPS64-NEXT: sra $1, $1, 24 ; MIPS64-NEXT: # %bb.3: # %entry +; MIPS64-NEXT: sll $1, $1, 24 ; MIPS64-NEXT: jr $ra -; MIPS64-NEXT: nop +; MIPS64-NEXT: sra $2, $1, 24 ; ; MIPS64R2-LABEL: AtomicLoadSub8: ; MIPS64R2: # %bb.0: # %entry @@ -2986,30 +3003,30 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8))) ; MIPS64R2-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R2-NEXT: daddiu $2, $zero, -4 -; MIPS64R2-NEXT: and $3, $1, $2 +; MIPS64R2-NEXT: and $2, $1, $2 ; MIPS64R2-NEXT: andi $1, $1, 3 -; MIPS64R2-NEXT: sll $1, $1, 3 -; MIPS64R2-NEXT: ori $2, $zero, 255 -; MIPS64R2-NEXT: sllv $5, $2, $1 +; MIPS64R2-NEXT: sll $3, $1, 3 +; MIPS64R2-NEXT: ori $1, $zero, 255 +; MIPS64R2-NEXT: sllv $5, $1, $3 ; MIPS64R2-NEXT: nor $6, $zero, $5 -; MIPS64R2-NEXT: sllv $4, $4, $1 +; MIPS64R2-NEXT: sllv $4, $4, $3 ; MIPS64R2-NEXT: .LBB9_1: # %entry ; MIPS64R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R2-NEXT: ll $7, 0($3) +; MIPS64R2-NEXT: ll $7, 0($2) ; MIPS64R2-NEXT: subu $8, $7, $4 ; MIPS64R2-NEXT: and $8, $8, $5 ; MIPS64R2-NEXT: and $9, $7, $6 ; MIPS64R2-NEXT: or $9, $9, $8 -; MIPS64R2-NEXT: sc $9, 0($3) +; MIPS64R2-NEXT: sc $9, 0($2) ; MIPS64R2-NEXT: beqz $9, .LBB9_1 ; MIPS64R2-NEXT: nop ; MIPS64R2-NEXT: # %bb.2: # %entry -; MIPS64R2-NEXT: and $2, $7, $5 -; MIPS64R2-NEXT: srlv $2, $2, $1 -; MIPS64R2-NEXT: seb $2, $2 +; MIPS64R2-NEXT: and $1, $7, $5 +; MIPS64R2-NEXT: srlv $1, $1, $3 +; MIPS64R2-NEXT: seb $1, $1 ; MIPS64R2-NEXT: # %bb.3: # %entry ; MIPS64R2-NEXT: jr $ra -; MIPS64R2-NEXT: nop +; MIPS64R2-NEXT: seb $2, $1 ; ; MIPS64R6-LABEL: AtomicLoadSub8: ; MIPS64R6: # %bb.0: # %entry @@ -3018,28 +3035,29 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub8))) ; MIPS64R6-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R6-NEXT: daddiu $2, $zero, -4 -; MIPS64R6-NEXT: and $3, $1, $2 +; MIPS64R6-NEXT: and $2, $1, $2 ; MIPS64R6-NEXT: andi $1, $1, 3 -; MIPS64R6-NEXT: sll $1, $1, 3 -; MIPS64R6-NEXT: ori $2, $zero, 255 -; MIPS64R6-NEXT: sllv $5, $2, $1 +; MIPS64R6-NEXT: sll $3, $1, 3 +; MIPS64R6-NEXT: ori $1, $zero, 255 +; MIPS64R6-NEXT: sllv $5, $1, $3 ; MIPS64R6-NEXT: nor $6, $zero, $5 -; MIPS64R6-NEXT: sllv $4, $4, $1 +; MIPS64R6-NEXT: sllv $4, $4, $3 ; MIPS64R6-NEXT: .LBB9_1: # %entry ; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R6-NEXT: ll $7, 0($3) +; MIPS64R6-NEXT: ll $7, 0($2) ; MIPS64R6-NEXT: subu $8, $7, $4 ; MIPS64R6-NEXT: and $8, $8, $5 ; MIPS64R6-NEXT: and $9, $7, $6 ; MIPS64R6-NEXT: or $9, $9, $8 -; MIPS64R6-NEXT: sc $9, 0($3) +; MIPS64R6-NEXT: sc $9, 0($2) ; MIPS64R6-NEXT: beqzc $9, .LBB9_1 ; MIPS64R6-NEXT: # %bb.2: # %entry -; MIPS64R6-NEXT: and $2, $7, $5 -; MIPS64R6-NEXT: srlv $2, $2, $1 -; MIPS64R6-NEXT: seb $2, $2 +; MIPS64R6-NEXT: and $1, $7, $5 +; MIPS64R6-NEXT: srlv $1, $1, $3 +; MIPS64R6-NEXT: seb $1, $1 ; MIPS64R6-NEXT: # %bb.3: # %entry -; MIPS64R6-NEXT: jrc $ra +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seb $2, $1 ; ; MIPS64R6O0-LABEL: AtomicLoadSub8: ; MIPS64R6O0: # %bb.0: # %entry @@ -3074,7 +3092,8 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS64R6O0-NEXT: # %bb.3: # %entry ; MIPS64R6O0-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64R6O0-NEXT: # %bb.4: # %entry -; MIPS64R6O0-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: lw $1, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: seb $2, $1 ; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16 ; MIPS64R6O0-NEXT: jrc $ra ; @@ -3085,28 +3104,29 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MM32-NEXT: addu $2, $2, $25 ; MM32-NEXT: lw $1, %got(y)($2) ; MM32-NEXT: addiu $2, $zero, -4 -; MM32-NEXT: and $3, $1, $2 +; MM32-NEXT: and $2, $1, $2 ; MM32-NEXT: andi $1, $1, 3 -; MM32-NEXT: sll $1, $1, 3 -; MM32-NEXT: ori $2, $zero, 255 -; MM32-NEXT: sllv $5, $2, $1 +; MM32-NEXT: sll $3, $1, 3 +; MM32-NEXT: ori $1, $zero, 255 +; MM32-NEXT: sllv $5, $1, $3 ; MM32-NEXT: nor $6, $zero, $5 -; MM32-NEXT: sllv $4, $4, $1 +; MM32-NEXT: sllv $4, $4, $3 ; MM32-NEXT: $BB9_1: # %entry ; MM32-NEXT: # =>This Inner Loop Header: Depth=1 -; MM32-NEXT: ll $7, 0($3) +; MM32-NEXT: ll $7, 0($2) ; MM32-NEXT: subu $8, $7, $4 ; MM32-NEXT: and $8, $8, $5 ; MM32-NEXT: and $9, $7, $6 ; MM32-NEXT: or $9, $9, $8 -; MM32-NEXT: sc $9, 0($3) +; MM32-NEXT: sc $9, 0($2) ; MM32-NEXT: beqzc $9, $BB9_1 ; MM32-NEXT: # %bb.2: # %entry -; MM32-NEXT: and $2, $7, $5 -; MM32-NEXT: srlv $2, $2, $1 -; MM32-NEXT: seb $2, $2 +; MM32-NEXT: and $1, $7, $5 +; MM32-NEXT: srlv $1, $1, $3 +; MM32-NEXT: seb $1, $1 ; MM32-NEXT: # %bb.3: # %entry -; MM32-NEXT: jrc $ra +; MM32-NEXT: jr $ra +; MM32-NEXT: seb $2, $1 ; ; O1-LABEL: AtomicLoadSub8: ; O1: # %bb.0: # %entry @@ -3115,31 +3135,32 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; O1-NEXT: addu $1, $2, $25 ; O1-NEXT: lw $1, %got(y)($1) ; O1-NEXT: addiu $2, $zero, -4 -; O1-NEXT: and $3, $1, $2 +; O1-NEXT: and $2, $1, $2 ; O1-NEXT: andi $1, $1, 3 -; O1-NEXT: sll $1, $1, 3 -; O1-NEXT: ori $2, $zero, 255 -; O1-NEXT: sllv $5, $2, $1 +; O1-NEXT: sll $3, $1, 3 +; O1-NEXT: ori $1, $zero, 255 +; O1-NEXT: sllv $5, $1, $3 ; O1-NEXT: nor $6, $zero, $5 -; O1-NEXT: sllv $4, $4, $1 +; O1-NEXT: sllv $4, $4, $3 ; O1-NEXT: $BB9_1: # %entry ; O1-NEXT: # =>This Inner Loop Header: Depth=1 -; O1-NEXT: ll $7, 0($3) +; O1-NEXT: ll $7, 0($2) ; O1-NEXT: subu $8, $7, $4 ; O1-NEXT: and $8, $8, $5 ; O1-NEXT: and $9, $7, $6 ; O1-NEXT: or $9, $9, $8 -; O1-NEXT: sc $9, 0($3) +; O1-NEXT: sc $9, 0($2) ; O1-NEXT: beqz $9, $BB9_1 ; O1-NEXT: nop ; O1-NEXT: # %bb.2: # %entry -; O1-NEXT: and $2, $7, $5 -; O1-NEXT: srlv $2, $2, $1 -; O1-NEXT: sll $2, $2, 24 -; O1-NEXT: sra $2, $2, 24 +; O1-NEXT: and $1, $7, $5 +; O1-NEXT: srlv $1, $1, $3 +; O1-NEXT: sll $1, $1, 24 +; O1-NEXT: sra $1, $1, 24 ; O1-NEXT: # %bb.3: # %entry +; O1-NEXT: sll $1, $1, 24 ; O1-NEXT: jr $ra -; O1-NEXT: nop +; O1-NEXT: sra $2, $1, 24 ; ; O2-LABEL: AtomicLoadSub8: ; O2: # %bb.0: # %entry @@ -3148,31 +3169,32 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; O2-NEXT: addu $1, $2, $25 ; O2-NEXT: lw $1, %got(y)($1) ; O2-NEXT: addiu $2, $zero, -4 -; O2-NEXT: and $3, $1, $2 +; O2-NEXT: and $2, $1, $2 ; O2-NEXT: andi $1, $1, 3 -; O2-NEXT: sll $1, $1, 3 -; O2-NEXT: ori $2, $zero, 255 -; O2-NEXT: sllv $5, $2, $1 +; O2-NEXT: sll $3, $1, 3 +; O2-NEXT: ori $1, $zero, 255 +; O2-NEXT: sllv $5, $1, $3 ; O2-NEXT: nor $6, $zero, $5 -; O2-NEXT: sllv $4, $4, $1 +; O2-NEXT: sllv $4, $4, $3 ; O2-NEXT: $BB9_1: # %entry ; O2-NEXT: # =>This Inner Loop Header: Depth=1 -; O2-NEXT: ll $7, 0($3) +; O2-NEXT: ll $7, 0($2) ; O2-NEXT: subu $8, $7, $4 ; O2-NEXT: and $8, $8, $5 ; O2-NEXT: and $9, $7, $6 ; O2-NEXT: or $9, $9, $8 -; O2-NEXT: sc $9, 0($3) +; O2-NEXT: sc $9, 0($2) ; O2-NEXT: beqz $9, $BB9_1 ; O2-NEXT: nop ; O2-NEXT: # %bb.2: # %entry -; O2-NEXT: and $2, $7, $5 -; O2-NEXT: srlv $2, $2, $1 -; O2-NEXT: sll $2, $2, 24 -; O2-NEXT: sra $2, $2, 24 +; O2-NEXT: and $1, $7, $5 +; O2-NEXT: srlv $1, $1, $3 +; O2-NEXT: sll $1, $1, 24 +; O2-NEXT: sra $1, $1, 24 ; O2-NEXT: # %bb.3: # %entry +; O2-NEXT: sll $1, $1, 24 ; O2-NEXT: jr $ra -; O2-NEXT: nop +; O2-NEXT: sra $2, $1, 24 ; ; O3-LABEL: AtomicLoadSub8: ; O3: # %bb.0: # %entry @@ -3181,31 +3203,32 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; O3-NEXT: addu $1, $2, $25 ; O3-NEXT: addiu $2, $zero, -4 ; O3-NEXT: lw $1, %got(y)($1) -; O3-NEXT: and $3, $1, $2 +; O3-NEXT: and $2, $1, $2 ; O3-NEXT: andi $1, $1, 3 -; O3-NEXT: ori $2, $zero, 255 -; O3-NEXT: sll $1, $1, 3 -; O3-NEXT: sllv $5, $2, $1 -; O3-NEXT: sllv $4, $4, $1 +; O3-NEXT: sll $3, $1, 3 +; O3-NEXT: ori $1, $zero, 255 +; O3-NEXT: sllv $5, $1, $3 +; O3-NEXT: sllv $4, $4, $3 ; O3-NEXT: nor $6, $zero, $5 ; O3-NEXT: $BB9_1: # %entry ; O3-NEXT: # =>This Inner Loop Header: Depth=1 -; O3-NEXT: ll $7, 0($3) +; O3-NEXT: ll $7, 0($2) ; O3-NEXT: subu $8, $7, $4 ; O3-NEXT: and $8, $8, $5 ; O3-NEXT: and $9, $7, $6 ; O3-NEXT: or $9, $9, $8 -; O3-NEXT: sc $9, 0($3) +; O3-NEXT: sc $9, 0($2) ; O3-NEXT: beqz $9, $BB9_1 ; O3-NEXT: nop ; O3-NEXT: # %bb.2: # %entry -; O3-NEXT: and $2, $7, $5 -; O3-NEXT: srlv $2, $2, $1 -; O3-NEXT: sll $2, $2, 24 -; O3-NEXT: sra $2, $2, 24 +; O3-NEXT: and $1, $7, $5 +; O3-NEXT: srlv $1, $1, $3 +; O3-NEXT: sll $1, $1, 24 +; O3-NEXT: sra $1, $1, 24 ; O3-NEXT: # %bb.3: # %entry +; O3-NEXT: sll $1, $1, 24 ; O3-NEXT: jr $ra -; O3-NEXT: nop +; O3-NEXT: sra $2, $1, 24 ; ; MIPS32EB-LABEL: AtomicLoadSub8: ; MIPS32EB: # %bb.0: # %entry @@ -3214,32 +3237,33 @@ define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { ; MIPS32EB-NEXT: addu $1, $2, $25 ; MIPS32EB-NEXT: lw $1, %got(y)($1) ; MIPS32EB-NEXT: addiu $2, $zero, -4 -; MIPS32EB-NEXT: and $3, $1, $2 +; MIPS32EB-NEXT: and $2, $1, $2 ; MIPS32EB-NEXT: andi $1, $1, 3 ; MIPS32EB-NEXT: xori $1, $1, 3 -; MIPS32EB-NEXT: sll $1, $1, 3 -; MIPS32EB-NEXT: ori $2, $zero, 255 -; MIPS32EB-NEXT: sllv $5, $2, $1 +; MIPS32EB-NEXT: sll $3, $1, 3 +; MIPS32EB-NEXT: ori $1, $zero, 255 +; MIPS32EB-NEXT: sllv $5, $1, $3 ; MIPS32EB-NEXT: nor $6, $zero, $5 -; MIPS32EB-NEXT: sllv $4, $4, $1 +; MIPS32EB-NEXT: sllv $4, $4, $3 ; MIPS32EB-NEXT: $BB9_1: # %entry ; MIPS32EB-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32EB-NEXT: ll $7, 0($3) +; MIPS32EB-NEXT: ll $7, 0($2) ; MIPS32EB-NEXT: subu $8, $7, $4 ; MIPS32EB-NEXT: and $8, $8, $5 ; MIPS32EB-NEXT: and $9, $7, $6 ; MIPS32EB-NEXT: or $9, $9, $8 -; MIPS32EB-NEXT: sc $9, 0($3) +; MIPS32EB-NEXT: sc $9, 0($2) ; MIPS32EB-NEXT: beqz $9, $BB9_1 ; MIPS32EB-NEXT: nop ; MIPS32EB-NEXT: # %bb.2: # %entry -; MIPS32EB-NEXT: and $2, $7, $5 -; MIPS32EB-NEXT: srlv $2, $2, $1 -; MIPS32EB-NEXT: sll $2, $2, 24 -; MIPS32EB-NEXT: sra $2, $2, 24 +; MIPS32EB-NEXT: and $1, $7, $5 +; MIPS32EB-NEXT: srlv $1, $1, $3 +; MIPS32EB-NEXT: sll $1, $1, 24 +; MIPS32EB-NEXT: sra $1, $1, 24 ; MIPS32EB-NEXT: # %bb.3: # %entry +; MIPS32EB-NEXT: sll $1, $1, 24 ; MIPS32EB-NEXT: jr $ra -; MIPS32EB-NEXT: nop +; MIPS32EB-NEXT: sra $2, $1, 24 entry: %0 = atomicrmw sub i8* @y, i8 %incr monotonic ret i8 %0 @@ -3254,32 +3278,33 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS32-NEXT: addu $1, $2, $25 ; MIPS32-NEXT: lw $1, %got(y)($1) ; MIPS32-NEXT: addiu $2, $zero, -4 -; MIPS32-NEXT: and $3, $1, $2 +; MIPS32-NEXT: and $2, $1, $2 ; MIPS32-NEXT: andi $1, $1, 3 -; MIPS32-NEXT: sll $1, $1, 3 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: sllv $5, $2, $1 +; MIPS32-NEXT: sll $3, $1, 3 +; MIPS32-NEXT: ori $1, $zero, 255 +; MIPS32-NEXT: sllv $5, $1, $3 ; MIPS32-NEXT: nor $6, $zero, $5 -; MIPS32-NEXT: sllv $4, $4, $1 +; MIPS32-NEXT: sllv $4, $4, $3 ; MIPS32-NEXT: $BB10_1: # %entry ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $7, 0($3) +; MIPS32-NEXT: ll $7, 0($2) ; MIPS32-NEXT: and $8, $7, $4 ; MIPS32-NEXT: nor $8, $zero, $8 ; MIPS32-NEXT: and $8, $8, $5 ; MIPS32-NEXT: and $9, $7, $6 ; MIPS32-NEXT: or $9, $9, $8 -; MIPS32-NEXT: sc $9, 0($3) +; MIPS32-NEXT: sc $9, 0($2) ; MIPS32-NEXT: beqz $9, $BB10_1 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $2, $7, $5 -; MIPS32-NEXT: srlv $2, $2, $1 -; MIPS32-NEXT: sll $2, $2, 24 -; MIPS32-NEXT: sra $2, $2, 24 +; MIPS32-NEXT: and $1, $7, $5 +; MIPS32-NEXT: srlv $1, $1, $3 +; MIPS32-NEXT: sll $1, $1, 24 +; MIPS32-NEXT: sra $1, $1, 24 ; MIPS32-NEXT: # %bb.3: # %entry +; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; MIPS32-NEXT: sra $2, $1, 24 ; ; MIPS32O0-LABEL: AtomicLoadNand8: ; MIPS32O0: # %bb.0: # %entry @@ -3329,31 +3354,31 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS32R2-NEXT: addu $1, $2, $25 ; MIPS32R2-NEXT: lw $1, %got(y)($1) ; MIPS32R2-NEXT: addiu $2, $zero, -4 -; MIPS32R2-NEXT: and $3, $1, $2 +; MIPS32R2-NEXT: and $2, $1, $2 ; MIPS32R2-NEXT: andi $1, $1, 3 -; MIPS32R2-NEXT: sll $1, $1, 3 -; MIPS32R2-NEXT: ori $2, $zero, 255 -; MIPS32R2-NEXT: sllv $5, $2, $1 +; MIPS32R2-NEXT: sll $3, $1, 3 +; MIPS32R2-NEXT: ori $1, $zero, 255 +; MIPS32R2-NEXT: sllv $5, $1, $3 ; MIPS32R2-NEXT: nor $6, $zero, $5 -; MIPS32R2-NEXT: sllv $4, $4, $1 +; MIPS32R2-NEXT: sllv $4, $4, $3 ; MIPS32R2-NEXT: $BB10_1: # %entry ; MIPS32R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R2-NEXT: ll $7, 0($3) +; MIPS32R2-NEXT: ll $7, 0($2) ; MIPS32R2-NEXT: and $8, $7, $4 ; MIPS32R2-NEXT: nor $8, $zero, $8 ; MIPS32R2-NEXT: and $8, $8, $5 ; MIPS32R2-NEXT: and $9, $7, $6 ; MIPS32R2-NEXT: or $9, $9, $8 -; MIPS32R2-NEXT: sc $9, 0($3) +; MIPS32R2-NEXT: sc $9, 0($2) ; MIPS32R2-NEXT: beqz $9, $BB10_1 ; MIPS32R2-NEXT: nop ; MIPS32R2-NEXT: # %bb.2: # %entry -; MIPS32R2-NEXT: and $2, $7, $5 -; MIPS32R2-NEXT: srlv $2, $2, $1 -; MIPS32R2-NEXT: seb $2, $2 +; MIPS32R2-NEXT: and $1, $7, $5 +; MIPS32R2-NEXT: srlv $1, $1, $3 +; MIPS32R2-NEXT: seb $1, $1 ; MIPS32R2-NEXT: # %bb.3: # %entry ; MIPS32R2-NEXT: jr $ra -; MIPS32R2-NEXT: nop +; MIPS32R2-NEXT: seb $2, $1 ; ; MIPS32R6-LABEL: AtomicLoadNand8: ; MIPS32R6: # %bb.0: # %entry @@ -3362,29 +3387,30 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS32R6-NEXT: addu $1, $2, $25 ; MIPS32R6-NEXT: lw $1, %got(y)($1) ; MIPS32R6-NEXT: addiu $2, $zero, -4 -; MIPS32R6-NEXT: and $3, $1, $2 +; MIPS32R6-NEXT: and $2, $1, $2 ; MIPS32R6-NEXT: andi $1, $1, 3 -; MIPS32R6-NEXT: sll $1, $1, 3 -; MIPS32R6-NEXT: ori $2, $zero, 255 -; MIPS32R6-NEXT: sllv $5, $2, $1 +; MIPS32R6-NEXT: sll $3, $1, 3 +; MIPS32R6-NEXT: ori $1, $zero, 255 +; MIPS32R6-NEXT: sllv $5, $1, $3 ; MIPS32R6-NEXT: nor $6, $zero, $5 -; MIPS32R6-NEXT: sllv $4, $4, $1 +; MIPS32R6-NEXT: sllv $4, $4, $3 ; MIPS32R6-NEXT: $BB10_1: # %entry ; MIPS32R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R6-NEXT: ll $7, 0($3) +; MIPS32R6-NEXT: ll $7, 0($2) ; MIPS32R6-NEXT: and $8, $7, $4 ; MIPS32R6-NEXT: nor $8, $zero, $8 ; MIPS32R6-NEXT: and $8, $8, $5 ; MIPS32R6-NEXT: and $9, $7, $6 ; MIPS32R6-NEXT: or $9, $9, $8 -; MIPS32R6-NEXT: sc $9, 0($3) +; MIPS32R6-NEXT: sc $9, 0($2) ; MIPS32R6-NEXT: beqzc $9, $BB10_1 ; MIPS32R6-NEXT: # %bb.2: # %entry -; MIPS32R6-NEXT: and $2, $7, $5 -; MIPS32R6-NEXT: srlv $2, $2, $1 -; MIPS32R6-NEXT: seb $2, $2 +; MIPS32R6-NEXT: and $1, $7, $5 +; MIPS32R6-NEXT: srlv $1, $1, $3 +; MIPS32R6-NEXT: seb $1, $1 ; MIPS32R6-NEXT: # %bb.3: # %entry -; MIPS32R6-NEXT: jrc $ra +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seb $2, $1 ; ; MIPS32R6O0-LABEL: AtomicLoadNand8: ; MIPS32R6O0: # %bb.0: # %entry @@ -3419,7 +3445,8 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS32R6O0-NEXT: # %bb.3: # %entry ; MIPS32R6O0-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS32R6O0-NEXT: # %bb.4: # %entry -; MIPS32R6O0-NEXT: lw $2, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: lw $1, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: seb $2, $1 ; MIPS32R6O0-NEXT: addiu $sp, $sp, 8 ; MIPS32R6O0-NEXT: jrc $ra ; @@ -3430,32 +3457,33 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS4-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8))) ; MIPS4-NEXT: ld $1, %got_disp(y)($1) ; MIPS4-NEXT: daddiu $2, $zero, -4 -; MIPS4-NEXT: and $3, $1, $2 +; MIPS4-NEXT: and $2, $1, $2 ; MIPS4-NEXT: andi $1, $1, 3 -; MIPS4-NEXT: sll $1, $1, 3 -; MIPS4-NEXT: ori $2, $zero, 255 -; MIPS4-NEXT: sllv $5, $2, $1 +; MIPS4-NEXT: sll $3, $1, 3 +; MIPS4-NEXT: ori $1, $zero, 255 +; MIPS4-NEXT: sllv $5, $1, $3 ; MIPS4-NEXT: nor $6, $zero, $5 -; MIPS4-NEXT: sllv $4, $4, $1 +; MIPS4-NEXT: sllv $4, $4, $3 ; MIPS4-NEXT: .LBB10_1: # %entry ; MIPS4-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS4-NEXT: ll $7, 0($3) +; MIPS4-NEXT: ll $7, 0($2) ; MIPS4-NEXT: and $8, $7, $4 ; MIPS4-NEXT: nor $8, $zero, $8 ; MIPS4-NEXT: and $8, $8, $5 ; MIPS4-NEXT: and $9, $7, $6 ; MIPS4-NEXT: or $9, $9, $8 -; MIPS4-NEXT: sc $9, 0($3) +; MIPS4-NEXT: sc $9, 0($2) ; MIPS4-NEXT: beqz $9, .LBB10_1 ; MIPS4-NEXT: nop ; MIPS4-NEXT: # %bb.2: # %entry -; MIPS4-NEXT: and $2, $7, $5 -; MIPS4-NEXT: srlv $2, $2, $1 -; MIPS4-NEXT: sll $2, $2, 24 -; MIPS4-NEXT: sra $2, $2, 24 +; MIPS4-NEXT: and $1, $7, $5 +; MIPS4-NEXT: srlv $1, $1, $3 +; MIPS4-NEXT: sll $1, $1, 24 +; MIPS4-NEXT: sra $1, $1, 24 ; MIPS4-NEXT: # %bb.3: # %entry +; MIPS4-NEXT: sll $1, $1, 24 ; MIPS4-NEXT: jr $ra -; MIPS4-NEXT: nop +; MIPS4-NEXT: sra $2, $1, 24 ; ; MIPS64-LABEL: AtomicLoadNand8: ; MIPS64: # %bb.0: # %entry @@ -3464,32 +3492,33 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8))) ; MIPS64-NEXT: ld $1, %got_disp(y)($1) ; MIPS64-NEXT: daddiu $2, $zero, -4 -; MIPS64-NEXT: and $3, $1, $2 +; MIPS64-NEXT: and $2, $1, $2 ; MIPS64-NEXT: andi $1, $1, 3 -; MIPS64-NEXT: sll $1, $1, 3 -; MIPS64-NEXT: ori $2, $zero, 255 -; MIPS64-NEXT: sllv $5, $2, $1 +; MIPS64-NEXT: sll $3, $1, 3 +; MIPS64-NEXT: ori $1, $zero, 255 +; MIPS64-NEXT: sllv $5, $1, $3 ; MIPS64-NEXT: nor $6, $zero, $5 -; MIPS64-NEXT: sllv $4, $4, $1 +; MIPS64-NEXT: sllv $4, $4, $3 ; MIPS64-NEXT: .LBB10_1: # %entry ; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64-NEXT: ll $7, 0($3) +; MIPS64-NEXT: ll $7, 0($2) ; MIPS64-NEXT: and $8, $7, $4 ; MIPS64-NEXT: nor $8, $zero, $8 ; MIPS64-NEXT: and $8, $8, $5 ; MIPS64-NEXT: and $9, $7, $6 ; MIPS64-NEXT: or $9, $9, $8 -; MIPS64-NEXT: sc $9, 0($3) +; MIPS64-NEXT: sc $9, 0($2) ; MIPS64-NEXT: beqz $9, .LBB10_1 ; MIPS64-NEXT: nop ; MIPS64-NEXT: # %bb.2: # %entry -; MIPS64-NEXT: and $2, $7, $5 -; MIPS64-NEXT: srlv $2, $2, $1 -; MIPS64-NEXT: sll $2, $2, 24 -; MIPS64-NEXT: sra $2, $2, 24 +; MIPS64-NEXT: and $1, $7, $5 +; MIPS64-NEXT: srlv $1, $1, $3 +; MIPS64-NEXT: sll $1, $1, 24 +; MIPS64-NEXT: sra $1, $1, 24 ; MIPS64-NEXT: # %bb.3: # %entry +; MIPS64-NEXT: sll $1, $1, 24 ; MIPS64-NEXT: jr $ra -; MIPS64-NEXT: nop +; MIPS64-NEXT: sra $2, $1, 24 ; ; MIPS64R2-LABEL: AtomicLoadNand8: ; MIPS64R2: # %bb.0: # %entry @@ -3498,31 +3527,31 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8))) ; MIPS64R2-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R2-NEXT: daddiu $2, $zero, -4 -; MIPS64R2-NEXT: and $3, $1, $2 +; MIPS64R2-NEXT: and $2, $1, $2 ; MIPS64R2-NEXT: andi $1, $1, 3 -; MIPS64R2-NEXT: sll $1, $1, 3 -; MIPS64R2-NEXT: ori $2, $zero, 255 -; MIPS64R2-NEXT: sllv $5, $2, $1 +; MIPS64R2-NEXT: sll $3, $1, 3 +; MIPS64R2-NEXT: ori $1, $zero, 255 +; MIPS64R2-NEXT: sllv $5, $1, $3 ; MIPS64R2-NEXT: nor $6, $zero, $5 -; MIPS64R2-NEXT: sllv $4, $4, $1 +; MIPS64R2-NEXT: sllv $4, $4, $3 ; MIPS64R2-NEXT: .LBB10_1: # %entry ; MIPS64R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R2-NEXT: ll $7, 0($3) +; MIPS64R2-NEXT: ll $7, 0($2) ; MIPS64R2-NEXT: and $8, $7, $4 ; MIPS64R2-NEXT: nor $8, $zero, $8 ; MIPS64R2-NEXT: and $8, $8, $5 ; MIPS64R2-NEXT: and $9, $7, $6 ; MIPS64R2-NEXT: or $9, $9, $8 -; MIPS64R2-NEXT: sc $9, 0($3) +; MIPS64R2-NEXT: sc $9, 0($2) ; MIPS64R2-NEXT: beqz $9, .LBB10_1 ; MIPS64R2-NEXT: nop ; MIPS64R2-NEXT: # %bb.2: # %entry -; MIPS64R2-NEXT: and $2, $7, $5 -; MIPS64R2-NEXT: srlv $2, $2, $1 -; MIPS64R2-NEXT: seb $2, $2 +; MIPS64R2-NEXT: and $1, $7, $5 +; MIPS64R2-NEXT: srlv $1, $1, $3 +; MIPS64R2-NEXT: seb $1, $1 ; MIPS64R2-NEXT: # %bb.3: # %entry ; MIPS64R2-NEXT: jr $ra -; MIPS64R2-NEXT: nop +; MIPS64R2-NEXT: seb $2, $1 ; ; MIPS64R6-LABEL: AtomicLoadNand8: ; MIPS64R6: # %bb.0: # %entry @@ -3531,29 +3560,30 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand8))) ; MIPS64R6-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R6-NEXT: daddiu $2, $zero, -4 -; MIPS64R6-NEXT: and $3, $1, $2 +; MIPS64R6-NEXT: and $2, $1, $2 ; MIPS64R6-NEXT: andi $1, $1, 3 -; MIPS64R6-NEXT: sll $1, $1, 3 -; MIPS64R6-NEXT: ori $2, $zero, 255 -; MIPS64R6-NEXT: sllv $5, $2, $1 +; MIPS64R6-NEXT: sll $3, $1, 3 +; MIPS64R6-NEXT: ori $1, $zero, 255 +; MIPS64R6-NEXT: sllv $5, $1, $3 ; MIPS64R6-NEXT: nor $6, $zero, $5 -; MIPS64R6-NEXT: sllv $4, $4, $1 +; MIPS64R6-NEXT: sllv $4, $4, $3 ; MIPS64R6-NEXT: .LBB10_1: # %entry ; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R6-NEXT: ll $7, 0($3) +; MIPS64R6-NEXT: ll $7, 0($2) ; MIPS64R6-NEXT: and $8, $7, $4 ; MIPS64R6-NEXT: nor $8, $zero, $8 ; MIPS64R6-NEXT: and $8, $8, $5 ; MIPS64R6-NEXT: and $9, $7, $6 ; MIPS64R6-NEXT: or $9, $9, $8 -; MIPS64R6-NEXT: sc $9, 0($3) +; MIPS64R6-NEXT: sc $9, 0($2) ; MIPS64R6-NEXT: beqzc $9, .LBB10_1 ; MIPS64R6-NEXT: # %bb.2: # %entry -; MIPS64R6-NEXT: and $2, $7, $5 -; MIPS64R6-NEXT: srlv $2, $2, $1 -; MIPS64R6-NEXT: seb $2, $2 +; MIPS64R6-NEXT: and $1, $7, $5 +; MIPS64R6-NEXT: srlv $1, $1, $3 +; MIPS64R6-NEXT: seb $1, $1 ; MIPS64R6-NEXT: # %bb.3: # %entry -; MIPS64R6-NEXT: jrc $ra +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seb $2, $1 ; ; MIPS64R6O0-LABEL: AtomicLoadNand8: ; MIPS64R6O0: # %bb.0: # %entry @@ -3589,7 +3619,8 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS64R6O0-NEXT: # %bb.3: # %entry ; MIPS64R6O0-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64R6O0-NEXT: # %bb.4: # %entry -; MIPS64R6O0-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: lw $1, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: seb $2, $1 ; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16 ; MIPS64R6O0-NEXT: jrc $ra ; @@ -3600,29 +3631,30 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MM32-NEXT: addu $2, $2, $25 ; MM32-NEXT: lw $1, %got(y)($2) ; MM32-NEXT: addiu $2, $zero, -4 -; MM32-NEXT: and $3, $1, $2 +; MM32-NEXT: and $2, $1, $2 ; MM32-NEXT: andi $1, $1, 3 -; MM32-NEXT: sll $1, $1, 3 -; MM32-NEXT: ori $2, $zero, 255 -; MM32-NEXT: sllv $5, $2, $1 +; MM32-NEXT: sll $3, $1, 3 +; MM32-NEXT: ori $1, $zero, 255 +; MM32-NEXT: sllv $5, $1, $3 ; MM32-NEXT: nor $6, $zero, $5 -; MM32-NEXT: sllv $4, $4, $1 +; MM32-NEXT: sllv $4, $4, $3 ; MM32-NEXT: $BB10_1: # %entry ; MM32-NEXT: # =>This Inner Loop Header: Depth=1 -; MM32-NEXT: ll $7, 0($3) +; MM32-NEXT: ll $7, 0($2) ; MM32-NEXT: and $8, $7, $4 ; MM32-NEXT: nor $8, $zero, $8 ; MM32-NEXT: and $8, $8, $5 ; MM32-NEXT: and $9, $7, $6 ; MM32-NEXT: or $9, $9, $8 -; MM32-NEXT: sc $9, 0($3) +; MM32-NEXT: sc $9, 0($2) ; MM32-NEXT: beqzc $9, $BB10_1 ; MM32-NEXT: # %bb.2: # %entry -; MM32-NEXT: and $2, $7, $5 -; MM32-NEXT: srlv $2, $2, $1 -; MM32-NEXT: seb $2, $2 +; MM32-NEXT: and $1, $7, $5 +; MM32-NEXT: srlv $1, $1, $3 +; MM32-NEXT: seb $1, $1 ; MM32-NEXT: # %bb.3: # %entry -; MM32-NEXT: jrc $ra +; MM32-NEXT: jr $ra +; MM32-NEXT: seb $2, $1 ; ; O1-LABEL: AtomicLoadNand8: ; O1: # %bb.0: # %entry @@ -3631,32 +3663,33 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; O1-NEXT: addu $1, $2, $25 ; O1-NEXT: lw $1, %got(y)($1) ; O1-NEXT: addiu $2, $zero, -4 -; O1-NEXT: and $3, $1, $2 +; O1-NEXT: and $2, $1, $2 ; O1-NEXT: andi $1, $1, 3 -; O1-NEXT: sll $1, $1, 3 -; O1-NEXT: ori $2, $zero, 255 -; O1-NEXT: sllv $5, $2, $1 +; O1-NEXT: sll $3, $1, 3 +; O1-NEXT: ori $1, $zero, 255 +; O1-NEXT: sllv $5, $1, $3 ; O1-NEXT: nor $6, $zero, $5 -; O1-NEXT: sllv $4, $4, $1 +; O1-NEXT: sllv $4, $4, $3 ; O1-NEXT: $BB10_1: # %entry ; O1-NEXT: # =>This Inner Loop Header: Depth=1 -; O1-NEXT: ll $7, 0($3) +; O1-NEXT: ll $7, 0($2) ; O1-NEXT: and $8, $7, $4 ; O1-NEXT: nor $8, $zero, $8 ; O1-NEXT: and $8, $8, $5 ; O1-NEXT: and $9, $7, $6 ; O1-NEXT: or $9, $9, $8 -; O1-NEXT: sc $9, 0($3) +; O1-NEXT: sc $9, 0($2) ; O1-NEXT: beqz $9, $BB10_1 ; O1-NEXT: nop ; O1-NEXT: # %bb.2: # %entry -; O1-NEXT: and $2, $7, $5 -; O1-NEXT: srlv $2, $2, $1 -; O1-NEXT: sll $2, $2, 24 -; O1-NEXT: sra $2, $2, 24 +; O1-NEXT: and $1, $7, $5 +; O1-NEXT: srlv $1, $1, $3 +; O1-NEXT: sll $1, $1, 24 +; O1-NEXT: sra $1, $1, 24 ; O1-NEXT: # %bb.3: # %entry +; O1-NEXT: sll $1, $1, 24 ; O1-NEXT: jr $ra -; O1-NEXT: nop +; O1-NEXT: sra $2, $1, 24 ; ; O2-LABEL: AtomicLoadNand8: ; O2: # %bb.0: # %entry @@ -3665,32 +3698,33 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; O2-NEXT: addu $1, $2, $25 ; O2-NEXT: lw $1, %got(y)($1) ; O2-NEXT: addiu $2, $zero, -4 -; O2-NEXT: and $3, $1, $2 +; O2-NEXT: and $2, $1, $2 ; O2-NEXT: andi $1, $1, 3 -; O2-NEXT: sll $1, $1, 3 -; O2-NEXT: ori $2, $zero, 255 -; O2-NEXT: sllv $5, $2, $1 +; O2-NEXT: sll $3, $1, 3 +; O2-NEXT: ori $1, $zero, 255 +; O2-NEXT: sllv $5, $1, $3 ; O2-NEXT: nor $6, $zero, $5 -; O2-NEXT: sllv $4, $4, $1 +; O2-NEXT: sllv $4, $4, $3 ; O2-NEXT: $BB10_1: # %entry ; O2-NEXT: # =>This Inner Loop Header: Depth=1 -; O2-NEXT: ll $7, 0($3) +; O2-NEXT: ll $7, 0($2) ; O2-NEXT: and $8, $7, $4 ; O2-NEXT: nor $8, $zero, $8 ; O2-NEXT: and $8, $8, $5 ; O2-NEXT: and $9, $7, $6 ; O2-NEXT: or $9, $9, $8 -; O2-NEXT: sc $9, 0($3) +; O2-NEXT: sc $9, 0($2) ; O2-NEXT: beqz $9, $BB10_1 ; O2-NEXT: nop ; O2-NEXT: # %bb.2: # %entry -; O2-NEXT: and $2, $7, $5 -; O2-NEXT: srlv $2, $2, $1 -; O2-NEXT: sll $2, $2, 24 -; O2-NEXT: sra $2, $2, 24 +; O2-NEXT: and $1, $7, $5 +; O2-NEXT: srlv $1, $1, $3 +; O2-NEXT: sll $1, $1, 24 +; O2-NEXT: sra $1, $1, 24 ; O2-NEXT: # %bb.3: # %entry +; O2-NEXT: sll $1, $1, 24 ; O2-NEXT: jr $ra -; O2-NEXT: nop +; O2-NEXT: sra $2, $1, 24 ; ; O3-LABEL: AtomicLoadNand8: ; O3: # %bb.0: # %entry @@ -3699,32 +3733,33 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; O3-NEXT: addu $1, $2, $25 ; O3-NEXT: addiu $2, $zero, -4 ; O3-NEXT: lw $1, %got(y)($1) -; O3-NEXT: and $3, $1, $2 +; O3-NEXT: and $2, $1, $2 ; O3-NEXT: andi $1, $1, 3 -; O3-NEXT: ori $2, $zero, 255 -; O3-NEXT: sll $1, $1, 3 -; O3-NEXT: sllv $5, $2, $1 -; O3-NEXT: sllv $4, $4, $1 +; O3-NEXT: sll $3, $1, 3 +; O3-NEXT: ori $1, $zero, 255 +; O3-NEXT: sllv $5, $1, $3 +; O3-NEXT: sllv $4, $4, $3 ; O3-NEXT: nor $6, $zero, $5 ; O3-NEXT: $BB10_1: # %entry ; O3-NEXT: # =>This Inner Loop Header: Depth=1 -; O3-NEXT: ll $7, 0($3) +; O3-NEXT: ll $7, 0($2) ; O3-NEXT: and $8, $7, $4 ; O3-NEXT: nor $8, $zero, $8 ; O3-NEXT: and $8, $8, $5 ; O3-NEXT: and $9, $7, $6 ; O3-NEXT: or $9, $9, $8 -; O3-NEXT: sc $9, 0($3) +; O3-NEXT: sc $9, 0($2) ; O3-NEXT: beqz $9, $BB10_1 ; O3-NEXT: nop ; O3-NEXT: # %bb.2: # %entry -; O3-NEXT: and $2, $7, $5 -; O3-NEXT: srlv $2, $2, $1 -; O3-NEXT: sll $2, $2, 24 -; O3-NEXT: sra $2, $2, 24 +; O3-NEXT: and $1, $7, $5 +; O3-NEXT: srlv $1, $1, $3 +; O3-NEXT: sll $1, $1, 24 +; O3-NEXT: sra $1, $1, 24 ; O3-NEXT: # %bb.3: # %entry +; O3-NEXT: sll $1, $1, 24 ; O3-NEXT: jr $ra -; O3-NEXT: nop +; O3-NEXT: sra $2, $1, 24 ; ; MIPS32EB-LABEL: AtomicLoadNand8: ; MIPS32EB: # %bb.0: # %entry @@ -3733,33 +3768,34 @@ define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { ; MIPS32EB-NEXT: addu $1, $2, $25 ; MIPS32EB-NEXT: lw $1, %got(y)($1) ; MIPS32EB-NEXT: addiu $2, $zero, -4 -; MIPS32EB-NEXT: and $3, $1, $2 +; MIPS32EB-NEXT: and $2, $1, $2 ; MIPS32EB-NEXT: andi $1, $1, 3 ; MIPS32EB-NEXT: xori $1, $1, 3 -; MIPS32EB-NEXT: sll $1, $1, 3 -; MIPS32EB-NEXT: ori $2, $zero, 255 -; MIPS32EB-NEXT: sllv $5, $2, $1 +; MIPS32EB-NEXT: sll $3, $1, 3 +; MIPS32EB-NEXT: ori $1, $zero, 255 +; MIPS32EB-NEXT: sllv $5, $1, $3 ; MIPS32EB-NEXT: nor $6, $zero, $5 -; MIPS32EB-NEXT: sllv $4, $4, $1 +; MIPS32EB-NEXT: sllv $4, $4, $3 ; MIPS32EB-NEXT: $BB10_1: # %entry ; MIPS32EB-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32EB-NEXT: ll $7, 0($3) +; MIPS32EB-NEXT: ll $7, 0($2) ; MIPS32EB-NEXT: and $8, $7, $4 ; MIPS32EB-NEXT: nor $8, $zero, $8 ; MIPS32EB-NEXT: and $8, $8, $5 ; MIPS32EB-NEXT: and $9, $7, $6 ; MIPS32EB-NEXT: or $9, $9, $8 -; MIPS32EB-NEXT: sc $9, 0($3) +; MIPS32EB-NEXT: sc $9, 0($2) ; MIPS32EB-NEXT: beqz $9, $BB10_1 ; MIPS32EB-NEXT: nop ; MIPS32EB-NEXT: # %bb.2: # %entry -; MIPS32EB-NEXT: and $2, $7, $5 -; MIPS32EB-NEXT: srlv $2, $2, $1 -; MIPS32EB-NEXT: sll $2, $2, 24 -; MIPS32EB-NEXT: sra $2, $2, 24 +; MIPS32EB-NEXT: and $1, $7, $5 +; MIPS32EB-NEXT: srlv $1, $1, $3 +; MIPS32EB-NEXT: sll $1, $1, 24 +; MIPS32EB-NEXT: sra $1, $1, 24 ; MIPS32EB-NEXT: # %bb.3: # %entry +; MIPS32EB-NEXT: sll $1, $1, 24 ; MIPS32EB-NEXT: jr $ra -; MIPS32EB-NEXT: nop +; MIPS32EB-NEXT: sra $2, $1, 24 entry: %0 = atomicrmw nand i8* @y, i8 %incr monotonic ret i8 %0 @@ -3774,30 +3810,31 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS32-NEXT: addu $1, $2, $25 ; MIPS32-NEXT: lw $1, %got(y)($1) ; MIPS32-NEXT: addiu $2, $zero, -4 -; MIPS32-NEXT: and $3, $1, $2 +; MIPS32-NEXT: and $2, $1, $2 ; MIPS32-NEXT: andi $1, $1, 3 -; MIPS32-NEXT: sll $1, $1, 3 -; MIPS32-NEXT: ori $2, $zero, 255 -; MIPS32-NEXT: sllv $5, $2, $1 +; MIPS32-NEXT: sll $3, $1, 3 +; MIPS32-NEXT: ori $1, $zero, 255 +; MIPS32-NEXT: sllv $5, $1, $3 ; MIPS32-NEXT: nor $6, $zero, $5 -; MIPS32-NEXT: sllv $4, $4, $1 +; MIPS32-NEXT: sllv $4, $4, $3 ; MIPS32-NEXT: $BB11_1: # %entry ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $7, 0($3) +; MIPS32-NEXT: ll $7, 0($2) ; MIPS32-NEXT: and $8, $4, $5 ; MIPS32-NEXT: and $9, $7, $6 ; MIPS32-NEXT: or $9, $9, $8 -; MIPS32-NEXT: sc $9, 0($3) +; MIPS32-NEXT: sc $9, 0($2) ; MIPS32-NEXT: beqz $9, $BB11_1 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $2, $7, $5 -; MIPS32-NEXT: srlv $2, $2, $1 -; MIPS32-NEXT: sll $2, $2, 24 -; MIPS32-NEXT: sra $2, $2, 24 +; MIPS32-NEXT: and $1, $7, $5 +; MIPS32-NEXT: srlv $1, $1, $3 +; MIPS32-NEXT: sll $1, $1, 24 +; MIPS32-NEXT: sra $1, $1, 24 ; MIPS32-NEXT: # %bb.3: # %entry +; MIPS32-NEXT: sll $1, $1, 24 ; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; MIPS32-NEXT: sra $2, $1, 24 ; ; MIPS32O0-LABEL: AtomicSwap8: ; MIPS32O0: # %bb.0: # %entry @@ -3845,29 +3882,29 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS32R2-NEXT: addu $1, $2, $25 ; MIPS32R2-NEXT: lw $1, %got(y)($1) ; MIPS32R2-NEXT: addiu $2, $zero, -4 -; MIPS32R2-NEXT: and $3, $1, $2 +; MIPS32R2-NEXT: and $2, $1, $2 ; MIPS32R2-NEXT: andi $1, $1, 3 -; MIPS32R2-NEXT: sll $1, $1, 3 -; MIPS32R2-NEXT: ori $2, $zero, 255 -; MIPS32R2-NEXT: sllv $5, $2, $1 +; MIPS32R2-NEXT: sll $3, $1, 3 +; MIPS32R2-NEXT: ori $1, $zero, 255 +; MIPS32R2-NEXT: sllv $5, $1, $3 ; MIPS32R2-NEXT: nor $6, $zero, $5 -; MIPS32R2-NEXT: sllv $4, $4, $1 +; MIPS32R2-NEXT: sllv $4, $4, $3 ; MIPS32R2-NEXT: $BB11_1: # %entry ; MIPS32R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R2-NEXT: ll $7, 0($3) +; MIPS32R2-NEXT: ll $7, 0($2) ; MIPS32R2-NEXT: and $8, $4, $5 ; MIPS32R2-NEXT: and $9, $7, $6 ; MIPS32R2-NEXT: or $9, $9, $8 -; MIPS32R2-NEXT: sc $9, 0($3) +; MIPS32R2-NEXT: sc $9, 0($2) ; MIPS32R2-NEXT: beqz $9, $BB11_1 ; MIPS32R2-NEXT: nop ; MIPS32R2-NEXT: # %bb.2: # %entry -; MIPS32R2-NEXT: and $2, $7, $5 -; MIPS32R2-NEXT: srlv $2, $2, $1 -; MIPS32R2-NEXT: seb $2, $2 +; MIPS32R2-NEXT: and $1, $7, $5 +; MIPS32R2-NEXT: srlv $1, $1, $3 +; MIPS32R2-NEXT: seb $1, $1 ; MIPS32R2-NEXT: # %bb.3: # %entry ; MIPS32R2-NEXT: jr $ra -; MIPS32R2-NEXT: nop +; MIPS32R2-NEXT: seb $2, $1 ; ; MIPS32R6-LABEL: AtomicSwap8: ; MIPS32R6: # %bb.0: # %entry @@ -3876,27 +3913,28 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS32R6-NEXT: addu $1, $2, $25 ; MIPS32R6-NEXT: lw $1, %got(y)($1) ; MIPS32R6-NEXT: addiu $2, $zero, -4 -; MIPS32R6-NEXT: and $3, $1, $2 +; MIPS32R6-NEXT: and $2, $1, $2 ; MIPS32R6-NEXT: andi $1, $1, 3 -; MIPS32R6-NEXT: sll $1, $1, 3 -; MIPS32R6-NEXT: ori $2, $zero, 255 -; MIPS32R6-NEXT: sllv $5, $2, $1 +; MIPS32R6-NEXT: sll $3, $1, 3 +; MIPS32R6-NEXT: ori $1, $zero, 255 +; MIPS32R6-NEXT: sllv $5, $1, $3 ; MIPS32R6-NEXT: nor $6, $zero, $5 -; MIPS32R6-NEXT: sllv $4, $4, $1 +; MIPS32R6-NEXT: sllv $4, $4, $3 ; MIPS32R6-NEXT: $BB11_1: # %entry ; MIPS32R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R6-NEXT: ll $7, 0($3) +; MIPS32R6-NEXT: ll $7, 0($2) ; MIPS32R6-NEXT: and $8, $4, $5 ; MIPS32R6-NEXT: and $9, $7, $6 ; MIPS32R6-NEXT: or $9, $9, $8 -; MIPS32R6-NEXT: sc $9, 0($3) +; MIPS32R6-NEXT: sc $9, 0($2) ; MIPS32R6-NEXT: beqzc $9, $BB11_1 ; MIPS32R6-NEXT: # %bb.2: # %entry -; MIPS32R6-NEXT: and $2, $7, $5 -; MIPS32R6-NEXT: srlv $2, $2, $1 -; MIPS32R6-NEXT: seb $2, $2 +; MIPS32R6-NEXT: and $1, $7, $5 +; MIPS32R6-NEXT: srlv $1, $1, $3 +; MIPS32R6-NEXT: seb $1, $1 ; MIPS32R6-NEXT: # %bb.3: # %entry -; MIPS32R6-NEXT: jrc $ra +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seb $2, $1 ; ; MIPS32R6O0-LABEL: AtomicSwap8: ; MIPS32R6O0: # %bb.0: # %entry @@ -3929,7 +3967,8 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS32R6O0-NEXT: # %bb.3: # %entry ; MIPS32R6O0-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS32R6O0-NEXT: # %bb.4: # %entry -; MIPS32R6O0-NEXT: lw $2, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: lw $1, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: seb $2, $1 ; MIPS32R6O0-NEXT: addiu $sp, $sp, 8 ; MIPS32R6O0-NEXT: jrc $ra ; @@ -3940,30 +3979,31 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS4-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8))) ; MIPS4-NEXT: ld $1, %got_disp(y)($1) ; MIPS4-NEXT: daddiu $2, $zero, -4 -; MIPS4-NEXT: and $3, $1, $2 +; MIPS4-NEXT: and $2, $1, $2 ; MIPS4-NEXT: andi $1, $1, 3 -; MIPS4-NEXT: sll $1, $1, 3 -; MIPS4-NEXT: ori $2, $zero, 255 -; MIPS4-NEXT: sllv $5, $2, $1 +; MIPS4-NEXT: sll $3, $1, 3 +; MIPS4-NEXT: ori $1, $zero, 255 +; MIPS4-NEXT: sllv $5, $1, $3 ; MIPS4-NEXT: nor $6, $zero, $5 -; MIPS4-NEXT: sllv $4, $4, $1 +; MIPS4-NEXT: sllv $4, $4, $3 ; MIPS4-NEXT: .LBB11_1: # %entry ; MIPS4-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS4-NEXT: ll $7, 0($3) +; MIPS4-NEXT: ll $7, 0($2) ; MIPS4-NEXT: and $8, $4, $5 ; MIPS4-NEXT: and $9, $7, $6 ; MIPS4-NEXT: or $9, $9, $8 -; MIPS4-NEXT: sc $9, 0($3) +; MIPS4-NEXT: sc $9, 0($2) ; MIPS4-NEXT: beqz $9, .LBB11_1 ; MIPS4-NEXT: nop ; MIPS4-NEXT: # %bb.2: # %entry -; MIPS4-NEXT: and $2, $7, $5 -; MIPS4-NEXT: srlv $2, $2, $1 -; MIPS4-NEXT: sll $2, $2, 24 -; MIPS4-NEXT: sra $2, $2, 24 +; MIPS4-NEXT: and $1, $7, $5 +; MIPS4-NEXT: srlv $1, $1, $3 +; MIPS4-NEXT: sll $1, $1, 24 +; MIPS4-NEXT: sra $1, $1, 24 ; MIPS4-NEXT: # %bb.3: # %entry +; MIPS4-NEXT: sll $1, $1, 24 ; MIPS4-NEXT: jr $ra -; MIPS4-NEXT: nop +; MIPS4-NEXT: sra $2, $1, 24 ; ; MIPS64-LABEL: AtomicSwap8: ; MIPS64: # %bb.0: # %entry @@ -3972,30 +4012,31 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8))) ; MIPS64-NEXT: ld $1, %got_disp(y)($1) ; MIPS64-NEXT: daddiu $2, $zero, -4 -; MIPS64-NEXT: and $3, $1, $2 +; MIPS64-NEXT: and $2, $1, $2 ; MIPS64-NEXT: andi $1, $1, 3 -; MIPS64-NEXT: sll $1, $1, 3 -; MIPS64-NEXT: ori $2, $zero, 255 -; MIPS64-NEXT: sllv $5, $2, $1 +; MIPS64-NEXT: sll $3, $1, 3 +; MIPS64-NEXT: ori $1, $zero, 255 +; MIPS64-NEXT: sllv $5, $1, $3 ; MIPS64-NEXT: nor $6, $zero, $5 -; MIPS64-NEXT: sllv $4, $4, $1 +; MIPS64-NEXT: sllv $4, $4, $3 ; MIPS64-NEXT: .LBB11_1: # %entry ; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64-NEXT: ll $7, 0($3) +; MIPS64-NEXT: ll $7, 0($2) ; MIPS64-NEXT: and $8, $4, $5 ; MIPS64-NEXT: and $9, $7, $6 ; MIPS64-NEXT: or $9, $9, $8 -; MIPS64-NEXT: sc $9, 0($3) +; MIPS64-NEXT: sc $9, 0($2) ; MIPS64-NEXT: beqz $9, .LBB11_1 ; MIPS64-NEXT: nop ; MIPS64-NEXT: # %bb.2: # %entry -; MIPS64-NEXT: and $2, $7, $5 -; MIPS64-NEXT: srlv $2, $2, $1 -; MIPS64-NEXT: sll $2, $2, 24 -; MIPS64-NEXT: sra $2, $2, 24 +; MIPS64-NEXT: and $1, $7, $5 +; MIPS64-NEXT: srlv $1, $1, $3 +; MIPS64-NEXT: sll $1, $1, 24 +; MIPS64-NEXT: sra $1, $1, 24 ; MIPS64-NEXT: # %bb.3: # %entry +; MIPS64-NEXT: sll $1, $1, 24 ; MIPS64-NEXT: jr $ra -; MIPS64-NEXT: nop +; MIPS64-NEXT: sra $2, $1, 24 ; ; MIPS64R2-LABEL: AtomicSwap8: ; MIPS64R2: # %bb.0: # %entry @@ -4004,29 +4045,29 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8))) ; MIPS64R2-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R2-NEXT: daddiu $2, $zero, -4 -; MIPS64R2-NEXT: and $3, $1, $2 +; MIPS64R2-NEXT: and $2, $1, $2 ; MIPS64R2-NEXT: andi $1, $1, 3 -; MIPS64R2-NEXT: sll $1, $1, 3 -; MIPS64R2-NEXT: ori $2, $zero, 255 -; MIPS64R2-NEXT: sllv $5, $2, $1 +; MIPS64R2-NEXT: sll $3, $1, 3 +; MIPS64R2-NEXT: ori $1, $zero, 255 +; MIPS64R2-NEXT: sllv $5, $1, $3 ; MIPS64R2-NEXT: nor $6, $zero, $5 -; MIPS64R2-NEXT: sllv $4, $4, $1 +; MIPS64R2-NEXT: sllv $4, $4, $3 ; MIPS64R2-NEXT: .LBB11_1: # %entry ; MIPS64R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R2-NEXT: ll $7, 0($3) +; MIPS64R2-NEXT: ll $7, 0($2) ; MIPS64R2-NEXT: and $8, $4, $5 ; MIPS64R2-NEXT: and $9, $7, $6 ; MIPS64R2-NEXT: or $9, $9, $8 -; MIPS64R2-NEXT: sc $9, 0($3) +; MIPS64R2-NEXT: sc $9, 0($2) ; MIPS64R2-NEXT: beqz $9, .LBB11_1 ; MIPS64R2-NEXT: nop ; MIPS64R2-NEXT: # %bb.2: # %entry -; MIPS64R2-NEXT: and $2, $7, $5 -; MIPS64R2-NEXT: srlv $2, $2, $1 -; MIPS64R2-NEXT: seb $2, $2 +; MIPS64R2-NEXT: and $1, $7, $5 +; MIPS64R2-NEXT: srlv $1, $1, $3 +; MIPS64R2-NEXT: seb $1, $1 ; MIPS64R2-NEXT: # %bb.3: # %entry ; MIPS64R2-NEXT: jr $ra -; MIPS64R2-NEXT: nop +; MIPS64R2-NEXT: seb $2, $1 ; ; MIPS64R6-LABEL: AtomicSwap8: ; MIPS64R6: # %bb.0: # %entry @@ -4035,27 +4076,28 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap8))) ; MIPS64R6-NEXT: ld $1, %got_disp(y)($1) ; MIPS64R6-NEXT: daddiu $2, $zero, -4 -; MIPS64R6-NEXT: and $3, $1, $2 +; MIPS64R6-NEXT: and $2, $1, $2 ; MIPS64R6-NEXT: andi $1, $1, 3 -; MIPS64R6-NEXT: sll $1, $1, 3 -; MIPS64R6-NEXT: ori $2, $zero, 255 -; MIPS64R6-NEXT: sllv $5, $2, $1 +; MIPS64R6-NEXT: sll $3, $1, 3 +; MIPS64R6-NEXT: ori $1, $zero, 255 +; MIPS64R6-NEXT: sllv $5, $1, $3 ; MIPS64R6-NEXT: nor $6, $zero, $5 -; MIPS64R6-NEXT: sllv $4, $4, $1 +; MIPS64R6-NEXT: sllv $4, $4, $3 ; MIPS64R6-NEXT: .LBB11_1: # %entry ; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R6-NEXT: ll $7, 0($3) +; MIPS64R6-NEXT: ll $7, 0($2) ; MIPS64R6-NEXT: and $8, $4, $5 ; MIPS64R6-NEXT: and $9, $7, $6 ; MIPS64R6-NEXT: or $9, $9, $8 -; MIPS64R6-NEXT: sc $9, 0($3) +; MIPS64R6-NEXT: sc $9, 0($2) ; MIPS64R6-NEXT: beqzc $9, .LBB11_1 ; MIPS64R6-NEXT: # %bb.2: # %entry -; MIPS64R6-NEXT: and $2, $7, $5 -; MIPS64R6-NEXT: srlv $2, $2, $1 -; MIPS64R6-NEXT: seb $2, $2 +; MIPS64R6-NEXT: and $1, $7, $5 +; MIPS64R6-NEXT: srlv $1, $1, $3 +; MIPS64R6-NEXT: seb $1, $1 ; MIPS64R6-NEXT: # %bb.3: # %entry -; MIPS64R6-NEXT: jrc $ra +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seb $2, $1 ; ; MIPS64R6O0-LABEL: AtomicSwap8: ; MIPS64R6O0: # %bb.0: # %entry @@ -4089,7 +4131,8 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS64R6O0-NEXT: # %bb.3: # %entry ; MIPS64R6O0-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64R6O0-NEXT: # %bb.4: # %entry -; MIPS64R6O0-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: lw $1, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: seb $2, $1 ; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16 ; MIPS64R6O0-NEXT: jrc $ra ; @@ -4100,27 +4143,28 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MM32-NEXT: addu $2, $2, $25 ; MM32-NEXT: lw $1, %got(y)($2) ; MM32-NEXT: addiu $2, $zero, -4 -; MM32-NEXT: and $3, $1, $2 +; MM32-NEXT: and $2, $1, $2 ; MM32-NEXT: andi $1, $1, 3 -; MM32-NEXT: sll $1, $1, 3 -; MM32-NEXT: ori $2, $zero, 255 -; MM32-NEXT: sllv $5, $2, $1 +; MM32-NEXT: sll $3, $1, 3 +; MM32-NEXT: ori $1, $zero, 255 +; MM32-NEXT: sllv $5, $1, $3 ; MM32-NEXT: nor $6, $zero, $5 -; MM32-NEXT: sllv $4, $4, $1 +; MM32-NEXT: sllv $4, $4, $3 ; MM32-NEXT: $BB11_1: # %entry ; MM32-NEXT: # =>This Inner Loop Header: Depth=1 -; MM32-NEXT: ll $7, 0($3) +; MM32-NEXT: ll $7, 0($2) ; MM32-NEXT: and $8, $4, $5 ; MM32-NEXT: and $9, $7, $6 ; MM32-NEXT: or $9, $9, $8 -; MM32-NEXT: sc $9, 0($3) +; MM32-NEXT: sc $9, 0($2) ; MM32-NEXT: beqzc $9, $BB11_1 ; MM32-NEXT: # %bb.2: # %entry -; MM32-NEXT: and $2, $7, $5 -; MM32-NEXT: srlv $2, $2, $1 -; MM32-NEXT: seb $2, $2 +; MM32-NEXT: and $1, $7, $5 +; MM32-NEXT: srlv $1, $1, $3 +; MM32-NEXT: seb $1, $1 ; MM32-NEXT: # %bb.3: # %entry -; MM32-NEXT: jrc $ra +; MM32-NEXT: jr $ra +; MM32-NEXT: seb $2, $1 ; ; O1-LABEL: AtomicSwap8: ; O1: # %bb.0: # %entry @@ -4129,30 +4173,31 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; O1-NEXT: addu $1, $2, $25 ; O1-NEXT: lw $1, %got(y)($1) ; O1-NEXT: addiu $2, $zero, -4 -; O1-NEXT: and $3, $1, $2 +; O1-NEXT: and $2, $1, $2 ; O1-NEXT: andi $1, $1, 3 -; O1-NEXT: sll $1, $1, 3 -; O1-NEXT: ori $2, $zero, 255 -; O1-NEXT: sllv $5, $2, $1 +; O1-NEXT: sll $3, $1, 3 +; O1-NEXT: ori $1, $zero, 255 +; O1-NEXT: sllv $5, $1, $3 ; O1-NEXT: nor $6, $zero, $5 -; O1-NEXT: sllv $4, $4, $1 +; O1-NEXT: sllv $4, $4, $3 ; O1-NEXT: $BB11_1: # %entry ; O1-NEXT: # =>This Inner Loop Header: Depth=1 -; O1-NEXT: ll $7, 0($3) +; O1-NEXT: ll $7, 0($2) ; O1-NEXT: and $8, $4, $5 ; O1-NEXT: and $9, $7, $6 ; O1-NEXT: or $9, $9, $8 -; O1-NEXT: sc $9, 0($3) +; O1-NEXT: sc $9, 0($2) ; O1-NEXT: beqz $9, $BB11_1 ; O1-NEXT: nop ; O1-NEXT: # %bb.2: # %entry -; O1-NEXT: and $2, $7, $5 -; O1-NEXT: srlv $2, $2, $1 -; O1-NEXT: sll $2, $2, 24 -; O1-NEXT: sra $2, $2, 24 +; O1-NEXT: and $1, $7, $5 +; O1-NEXT: srlv $1, $1, $3 +; O1-NEXT: sll $1, $1, 24 +; O1-NEXT: sra $1, $1, 24 ; O1-NEXT: # %bb.3: # %entry +; O1-NEXT: sll $1, $1, 24 ; O1-NEXT: jr $ra -; O1-NEXT: nop +; O1-NEXT: sra $2, $1, 24 ; ; O2-LABEL: AtomicSwap8: ; O2: # %bb.0: # %entry @@ -4161,30 +4206,31 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; O2-NEXT: addu $1, $2, $25 ; O2-NEXT: lw $1, %got(y)($1) ; O2-NEXT: addiu $2, $zero, -4 -; O2-NEXT: and $3, $1, $2 +; O2-NEXT: and $2, $1, $2 ; O2-NEXT: andi $1, $1, 3 -; O2-NEXT: sll $1, $1, 3 -; O2-NEXT: ori $2, $zero, 255 -; O2-NEXT: sllv $5, $2, $1 +; O2-NEXT: sll $3, $1, 3 +; O2-NEXT: ori $1, $zero, 255 +; O2-NEXT: sllv $5, $1, $3 ; O2-NEXT: nor $6, $zero, $5 -; O2-NEXT: sllv $4, $4, $1 +; O2-NEXT: sllv $4, $4, $3 ; O2-NEXT: $BB11_1: # %entry ; O2-NEXT: # =>This Inner Loop Header: Depth=1 -; O2-NEXT: ll $7, 0($3) +; O2-NEXT: ll $7, 0($2) ; O2-NEXT: and $8, $4, $5 ; O2-NEXT: and $9, $7, $6 ; O2-NEXT: or $9, $9, $8 -; O2-NEXT: sc $9, 0($3) +; O2-NEXT: sc $9, 0($2) ; O2-NEXT: beqz $9, $BB11_1 ; O2-NEXT: nop ; O2-NEXT: # %bb.2: # %entry -; O2-NEXT: and $2, $7, $5 -; O2-NEXT: srlv $2, $2, $1 -; O2-NEXT: sll $2, $2, 24 -; O2-NEXT: sra $2, $2, 24 +; O2-NEXT: and $1, $7, $5 +; O2-NEXT: srlv $1, $1, $3 +; O2-NEXT: sll $1, $1, 24 +; O2-NEXT: sra $1, $1, 24 ; O2-NEXT: # %bb.3: # %entry +; O2-NEXT: sll $1, $1, 24 ; O2-NEXT: jr $ra -; O2-NEXT: nop +; O2-NEXT: sra $2, $1, 24 ; ; O3-LABEL: AtomicSwap8: ; O3: # %bb.0: # %entry @@ -4193,30 +4239,31 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; O3-NEXT: addu $1, $2, $25 ; O3-NEXT: addiu $2, $zero, -4 ; O3-NEXT: lw $1, %got(y)($1) -; O3-NEXT: and $3, $1, $2 +; O3-NEXT: and $2, $1, $2 ; O3-NEXT: andi $1, $1, 3 -; O3-NEXT: ori $2, $zero, 255 -; O3-NEXT: sll $1, $1, 3 -; O3-NEXT: sllv $5, $2, $1 -; O3-NEXT: sllv $4, $4, $1 +; O3-NEXT: sll $3, $1, 3 +; O3-NEXT: ori $1, $zero, 255 +; O3-NEXT: sllv $5, $1, $3 +; O3-NEXT: sllv $4, $4, $3 ; O3-NEXT: nor $6, $zero, $5 ; O3-NEXT: $BB11_1: # %entry ; O3-NEXT: # =>This Inner Loop Header: Depth=1 -; O3-NEXT: ll $7, 0($3) +; O3-NEXT: ll $7, 0($2) ; O3-NEXT: and $8, $4, $5 ; O3-NEXT: and $9, $7, $6 ; O3-NEXT: or $9, $9, $8 -; O3-NEXT: sc $9, 0($3) +; O3-NEXT: sc $9, 0($2) ; O3-NEXT: beqz $9, $BB11_1 ; O3-NEXT: nop ; O3-NEXT: # %bb.2: # %entry -; O3-NEXT: and $2, $7, $5 -; O3-NEXT: srlv $2, $2, $1 -; O3-NEXT: sll $2, $2, 24 -; O3-NEXT: sra $2, $2, 24 +; O3-NEXT: and $1, $7, $5 +; O3-NEXT: srlv $1, $1, $3 +; O3-NEXT: sll $1, $1, 24 +; O3-NEXT: sra $1, $1, 24 ; O3-NEXT: # %bb.3: # %entry +; O3-NEXT: sll $1, $1, 24 ; O3-NEXT: jr $ra -; O3-NEXT: nop +; O3-NEXT: sra $2, $1, 24 ; ; MIPS32EB-LABEL: AtomicSwap8: ; MIPS32EB: # %bb.0: # %entry @@ -4225,31 +4272,32 @@ define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { ; MIPS32EB-NEXT: addu $1, $2, $25 ; MIPS32EB-NEXT: lw $1, %got(y)($1) ; MIPS32EB-NEXT: addiu $2, $zero, -4 -; MIPS32EB-NEXT: and $3, $1, $2 +; MIPS32EB-NEXT: and $2, $1, $2 ; MIPS32EB-NEXT: andi $1, $1, 3 ; MIPS32EB-NEXT: xori $1, $1, 3 -; MIPS32EB-NEXT: sll $1, $1, 3 -; MIPS32EB-NEXT: ori $2, $zero, 255 -; MIPS32EB-NEXT: sllv $5, $2, $1 +; MIPS32EB-NEXT: sll $3, $1, 3 +; MIPS32EB-NEXT: ori $1, $zero, 255 +; MIPS32EB-NEXT: sllv $5, $1, $3 ; MIPS32EB-NEXT: nor $6, $zero, $5 -; MIPS32EB-NEXT: sllv $4, $4, $1 +; MIPS32EB-NEXT: sllv $4, $4, $3 ; MIPS32EB-NEXT: $BB11_1: # %entry ; MIPS32EB-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32EB-NEXT: ll $7, 0($3) +; MIPS32EB-NEXT: ll $7, 0($2) ; MIPS32EB-NEXT: and $8, $4, $5 ; MIPS32EB-NEXT: and $9, $7, $6 ; MIPS32EB-NEXT: or $9, $9, $8 -; MIPS32EB-NEXT: sc $9, 0($3) +; MIPS32EB-NEXT: sc $9, 0($2) ; MIPS32EB-NEXT: beqz $9, $BB11_1 ; MIPS32EB-NEXT: nop ; MIPS32EB-NEXT: # %bb.2: # %entry -; MIPS32EB-NEXT: and $2, $7, $5 -; MIPS32EB-NEXT: srlv $2, $2, $1 -; MIPS32EB-NEXT: sll $2, $2, 24 -; MIPS32EB-NEXT: sra $2, $2, 24 +; MIPS32EB-NEXT: and $1, $7, $5 +; MIPS32EB-NEXT: srlv $1, $1, $3 +; MIPS32EB-NEXT: sll $1, $1, 24 +; MIPS32EB-NEXT: sra $1, $1, 24 ; MIPS32EB-NEXT: # %bb.3: # %entry +; MIPS32EB-NEXT: sll $1, $1, 24 ; MIPS32EB-NEXT: jr $ra -; MIPS32EB-NEXT: nop +; MIPS32EB-NEXT: sra $2, $1, 24 entry: %0 = atomicrmw xchg i8* @y, i8 %newval monotonic ret i8 %0 @@ -5403,31 +5451,32 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS32-NEXT: addu $1, $2, $25 ; MIPS32-NEXT: lw $1, %got(z)($1) ; MIPS32-NEXT: addiu $2, $zero, -4 -; MIPS32-NEXT: and $3, $1, $2 +; MIPS32-NEXT: and $2, $1, $2 ; MIPS32-NEXT: andi $1, $1, 3 -; MIPS32-NEXT: sll $1, $1, 3 -; MIPS32-NEXT: ori $2, $zero, 65535 -; MIPS32-NEXT: sllv $5, $2, $1 +; MIPS32-NEXT: sll $3, $1, 3 +; MIPS32-NEXT: ori $1, $zero, 65535 +; MIPS32-NEXT: sllv $5, $1, $3 ; MIPS32-NEXT: nor $6, $zero, $5 -; MIPS32-NEXT: sllv $4, $4, $1 +; MIPS32-NEXT: sllv $4, $4, $3 ; MIPS32-NEXT: $BB14_1: # %entry ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32-NEXT: ll $7, 0($3) +; MIPS32-NEXT: ll $7, 0($2) ; MIPS32-NEXT: addu $8, $7, $4 ; MIPS32-NEXT: and $8, $8, $5 ; MIPS32-NEXT: and $9, $7, $6 ; MIPS32-NEXT: or $9, $9, $8 -; MIPS32-NEXT: sc $9, 0($3) +; MIPS32-NEXT: sc $9, 0($2) ; MIPS32-NEXT: beqz $9, $BB14_1 ; MIPS32-NEXT: nop ; MIPS32-NEXT: # %bb.2: # %entry -; MIPS32-NEXT: and $2, $7, $5 -; MIPS32-NEXT: srlv $2, $2, $1 -; MIPS32-NEXT: sll $2, $2, 16 -; MIPS32-NEXT: sra $2, $2, 16 +; MIPS32-NEXT: and $1, $7, $5 +; MIPS32-NEXT: srlv $1, $1, $3 +; MIPS32-NEXT: sll $1, $1, 16 +; MIPS32-NEXT: sra $1, $1, 16 ; MIPS32-NEXT: # %bb.3: # %entry +; MIPS32-NEXT: sll $1, $1, 16 ; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: nop +; MIPS32-NEXT: sra $2, $1, 16 ; ; MIPS32O0-LABEL: AtomicLoadAdd16: ; MIPS32O0: # %bb.0: # %entry @@ -5476,30 +5525,30 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS32R2-NEXT: addu $1, $2, $25 ; MIPS32R2-NEXT: lw $1, %got(z)($1) ; MIPS32R2-NEXT: addiu $2, $zero, -4 -; MIPS32R2-NEXT: and $3, $1, $2 +; MIPS32R2-NEXT: and $2, $1, $2 ; MIPS32R2-NEXT: andi $1, $1, 3 -; MIPS32R2-NEXT: sll $1, $1, 3 -; MIPS32R2-NEXT: ori $2, $zero, 65535 -; MIPS32R2-NEXT: sllv $5, $2, $1 +; MIPS32R2-NEXT: sll $3, $1, 3 +; MIPS32R2-NEXT: ori $1, $zero, 65535 +; MIPS32R2-NEXT: sllv $5, $1, $3 ; MIPS32R2-NEXT: nor $6, $zero, $5 -; MIPS32R2-NEXT: sllv $4, $4, $1 +; MIPS32R2-NEXT: sllv $4, $4, $3 ; MIPS32R2-NEXT: $BB14_1: # %entry ; MIPS32R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R2-NEXT: ll $7, 0($3) +; MIPS32R2-NEXT: ll $7, 0($2) ; MIPS32R2-NEXT: addu $8, $7, $4 ; MIPS32R2-NEXT: and $8, $8, $5 ; MIPS32R2-NEXT: and $9, $7, $6 ; MIPS32R2-NEXT: or $9, $9, $8 -; MIPS32R2-NEXT: sc $9, 0($3) +; MIPS32R2-NEXT: sc $9, 0($2) ; MIPS32R2-NEXT: beqz $9, $BB14_1 ; MIPS32R2-NEXT: nop ; MIPS32R2-NEXT: # %bb.2: # %entry -; MIPS32R2-NEXT: and $2, $7, $5 -; MIPS32R2-NEXT: srlv $2, $2, $1 -; MIPS32R2-NEXT: seh $2, $2 +; MIPS32R2-NEXT: and $1, $7, $5 +; MIPS32R2-NEXT: srlv $1, $1, $3 +; MIPS32R2-NEXT: seh $1, $1 ; MIPS32R2-NEXT: # %bb.3: # %entry ; MIPS32R2-NEXT: jr $ra -; MIPS32R2-NEXT: nop +; MIPS32R2-NEXT: seh $2, $1 ; ; MIPS32R6-LABEL: AtomicLoadAdd16: ; MIPS32R6: # %bb.0: # %entry @@ -5508,28 +5557,29 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS32R6-NEXT: addu $1, $2, $25 ; MIPS32R6-NEXT: lw $1, %got(z)($1) ; MIPS32R6-NEXT: addiu $2, $zero, -4 -; MIPS32R6-NEXT: and $3, $1, $2 +; MIPS32R6-NEXT: and $2, $1, $2 ; MIPS32R6-NEXT: andi $1, $1, 3 -; MIPS32R6-NEXT: sll $1, $1, 3 -; MIPS32R6-NEXT: ori $2, $zero, 65535 -; MIPS32R6-NEXT: sllv $5, $2, $1 +; MIPS32R6-NEXT: sll $3, $1, 3 +; MIPS32R6-NEXT: ori $1, $zero, 65535 +; MIPS32R6-NEXT: sllv $5, $1, $3 ; MIPS32R6-NEXT: nor $6, $zero, $5 -; MIPS32R6-NEXT: sllv $4, $4, $1 +; MIPS32R6-NEXT: sllv $4, $4, $3 ; MIPS32R6-NEXT: $BB14_1: # %entry ; MIPS32R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32R6-NEXT: ll $7, 0($3) +; MIPS32R6-NEXT: ll $7, 0($2) ; MIPS32R6-NEXT: addu $8, $7, $4 ; MIPS32R6-NEXT: and $8, $8, $5 ; MIPS32R6-NEXT: and $9, $7, $6 ; MIPS32R6-NEXT: or $9, $9, $8 -; MIPS32R6-NEXT: sc $9, 0($3) +; MIPS32R6-NEXT: sc $9, 0($2) ; MIPS32R6-NEXT: beqzc $9, $BB14_1 ; MIPS32R6-NEXT: # %bb.2: # %entry -; MIPS32R6-NEXT: and $2, $7, $5 -; MIPS32R6-NEXT: srlv $2, $2, $1 -; MIPS32R6-NEXT: seh $2, $2 +; MIPS32R6-NEXT: and $1, $7, $5 +; MIPS32R6-NEXT: srlv $1, $1, $3 +; MIPS32R6-NEXT: seh $1, $1 ; MIPS32R6-NEXT: # %bb.3: # %entry -; MIPS32R6-NEXT: jrc $ra +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: seh $2, $1 ; ; MIPS32R6O0-LABEL: AtomicLoadAdd16: ; MIPS32R6O0: # %bb.0: # %entry @@ -5563,7 +5613,8 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS32R6O0-NEXT: # %bb.3: # %entry ; MIPS32R6O0-NEXT: sw $1, 4($sp) # 4-byte Folded Spill ; MIPS32R6O0-NEXT: # %bb.4: # %entry -; MIPS32R6O0-NEXT: lw $2, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: lw $1, 4($sp) # 4-byte Folded Reload +; MIPS32R6O0-NEXT: seh $2, $1 ; MIPS32R6O0-NEXT: addiu $sp, $sp, 8 ; MIPS32R6O0-NEXT: jrc $ra ; @@ -5574,31 +5625,32 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS4-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16))) ; MIPS4-NEXT: ld $1, %got_disp(z)($1) ; MIPS4-NEXT: daddiu $2, $zero, -4 -; MIPS4-NEXT: and $3, $1, $2 +; MIPS4-NEXT: and $2, $1, $2 ; MIPS4-NEXT: andi $1, $1, 3 -; MIPS4-NEXT: sll $1, $1, 3 -; MIPS4-NEXT: ori $2, $zero, 65535 -; MIPS4-NEXT: sllv $5, $2, $1 +; MIPS4-NEXT: sll $3, $1, 3 +; MIPS4-NEXT: ori $1, $zero, 65535 +; MIPS4-NEXT: sllv $5, $1, $3 ; MIPS4-NEXT: nor $6, $zero, $5 -; MIPS4-NEXT: sllv $4, $4, $1 +; MIPS4-NEXT: sllv $4, $4, $3 ; MIPS4-NEXT: .LBB14_1: # %entry ; MIPS4-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS4-NEXT: ll $7, 0($3) +; MIPS4-NEXT: ll $7, 0($2) ; MIPS4-NEXT: addu $8, $7, $4 ; MIPS4-NEXT: and $8, $8, $5 ; MIPS4-NEXT: and $9, $7, $6 ; MIPS4-NEXT: or $9, $9, $8 -; MIPS4-NEXT: sc $9, 0($3) +; MIPS4-NEXT: sc $9, 0($2) ; MIPS4-NEXT: beqz $9, .LBB14_1 ; MIPS4-NEXT: nop ; MIPS4-NEXT: # %bb.2: # %entry -; MIPS4-NEXT: and $2, $7, $5 -; MIPS4-NEXT: srlv $2, $2, $1 -; MIPS4-NEXT: sll $2, $2, 16 -; MIPS4-NEXT: sra $2, $2, 16 +; MIPS4-NEXT: and $1, $7, $5 +; MIPS4-NEXT: srlv $1, $1, $3 +; MIPS4-NEXT: sll $1, $1, 16 +; MIPS4-NEXT: sra $1, $1, 16 ; MIPS4-NEXT: # %bb.3: # %entry +; MIPS4-NEXT: sll $1, $1, 16 ; MIPS4-NEXT: jr $ra -; MIPS4-NEXT: nop +; MIPS4-NEXT: sra $2, $1, 16 ; ; MIPS64-LABEL: AtomicLoadAdd16: ; MIPS64: # %bb.0: # %entry @@ -5607,31 +5659,32 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16))) ; MIPS64-NEXT: ld $1, %got_disp(z)($1) ; MIPS64-NEXT: daddiu $2, $zero, -4 -; MIPS64-NEXT: and $3, $1, $2 +; MIPS64-NEXT: and $2, $1, $2 ; MIPS64-NEXT: andi $1, $1, 3 -; MIPS64-NEXT: sll $1, $1, 3 -; MIPS64-NEXT: ori $2, $zero, 65535 -; MIPS64-NEXT: sllv $5, $2, $1 +; MIPS64-NEXT: sll $3, $1, 3 +; MIPS64-NEXT: ori $1, $zero, 65535 +; MIPS64-NEXT: sllv $5, $1, $3 ; MIPS64-NEXT: nor $6, $zero, $5 -; MIPS64-NEXT: sllv $4, $4, $1 +; MIPS64-NEXT: sllv $4, $4, $3 ; MIPS64-NEXT: .LBB14_1: # %entry ; MIPS64-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64-NEXT: ll $7, 0($3) +; MIPS64-NEXT: ll $7, 0($2) ; MIPS64-NEXT: addu $8, $7, $4 ; MIPS64-NEXT: and $8, $8, $5 ; MIPS64-NEXT: and $9, $7, $6 ; MIPS64-NEXT: or $9, $9, $8 -; MIPS64-NEXT: sc $9, 0($3) +; MIPS64-NEXT: sc $9, 0($2) ; MIPS64-NEXT: beqz $9, .LBB14_1 ; MIPS64-NEXT: nop ; MIPS64-NEXT: # %bb.2: # %entry -; MIPS64-NEXT: and $2, $7, $5 -; MIPS64-NEXT: srlv $2, $2, $1 -; MIPS64-NEXT: sll $2, $2, 16 -; MIPS64-NEXT: sra $2, $2, 16 +; MIPS64-NEXT: and $1, $7, $5 +; MIPS64-NEXT: srlv $1, $1, $3 +; MIPS64-NEXT: sll $1, $1, 16 +; MIPS64-NEXT: sra $1, $1, 16 ; MIPS64-NEXT: # %bb.3: # %entry +; MIPS64-NEXT: sll $1, $1, 16 ; MIPS64-NEXT: jr $ra -; MIPS64-NEXT: nop +; MIPS64-NEXT: sra $2, $1, 16 ; ; MIPS64R2-LABEL: AtomicLoadAdd16: ; MIPS64R2: # %bb.0: # %entry @@ -5640,30 +5693,30 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS64R2-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16))) ; MIPS64R2-NEXT: ld $1, %got_disp(z)($1) ; MIPS64R2-NEXT: daddiu $2, $zero, -4 -; MIPS64R2-NEXT: and $3, $1, $2 +; MIPS64R2-NEXT: and $2, $1, $2 ; MIPS64R2-NEXT: andi $1, $1, 3 -; MIPS64R2-NEXT: sll $1, $1, 3 -; MIPS64R2-NEXT: ori $2, $zero, 65535 -; MIPS64R2-NEXT: sllv $5, $2, $1 +; MIPS64R2-NEXT: sll $3, $1, 3 +; MIPS64R2-NEXT: ori $1, $zero, 65535 +; MIPS64R2-NEXT: sllv $5, $1, $3 ; MIPS64R2-NEXT: nor $6, $zero, $5 -; MIPS64R2-NEXT: sllv $4, $4, $1 +; MIPS64R2-NEXT: sllv $4, $4, $3 ; MIPS64R2-NEXT: .LBB14_1: # %entry ; MIPS64R2-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R2-NEXT: ll $7, 0($3) +; MIPS64R2-NEXT: ll $7, 0($2) ; MIPS64R2-NEXT: addu $8, $7, $4 ; MIPS64R2-NEXT: and $8, $8, $5 ; MIPS64R2-NEXT: and $9, $7, $6 ; MIPS64R2-NEXT: or $9, $9, $8 -; MIPS64R2-NEXT: sc $9, 0($3) +; MIPS64R2-NEXT: sc $9, 0($2) ; MIPS64R2-NEXT: beqz $9, .LBB14_1 ; MIPS64R2-NEXT: nop ; MIPS64R2-NEXT: # %bb.2: # %entry -; MIPS64R2-NEXT: and $2, $7, $5 -; MIPS64R2-NEXT: srlv $2, $2, $1 -; MIPS64R2-NEXT: seh $2, $2 +; MIPS64R2-NEXT: and $1, $7, $5 +; MIPS64R2-NEXT: srlv $1, $1, $3 +; MIPS64R2-NEXT: seh $1, $1 ; MIPS64R2-NEXT: # %bb.3: # %entry ; MIPS64R2-NEXT: jr $ra -; MIPS64R2-NEXT: nop +; MIPS64R2-NEXT: seh $2, $1 ; ; MIPS64R6-LABEL: AtomicLoadAdd16: ; MIPS64R6: # %bb.0: # %entry @@ -5672,28 +5725,29 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS64R6-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd16))) ; MIPS64R6-NEXT: ld $1, %got_disp(z)($1) ; MIPS64R6-NEXT: daddiu $2, $zero, -4 -; MIPS64R6-NEXT: and $3, $1, $2 +; MIPS64R6-NEXT: and $2, $1, $2 ; MIPS64R6-NEXT: andi $1, $1, 3 -; MIPS64R6-NEXT: sll $1, $1, 3 -; MIPS64R6-NEXT: ori $2, $zero, 65535 -; MIPS64R6-NEXT: sllv $5, $2, $1 +; MIPS64R6-NEXT: sll $3, $1, 3 +; MIPS64R6-NEXT: ori $1, $zero, 65535 +; MIPS64R6-NEXT: sllv $5, $1, $3 ; MIPS64R6-NEXT: nor $6, $zero, $5 -; MIPS64R6-NEXT: sllv $4, $4, $1 +; MIPS64R6-NEXT: sllv $4, $4, $3 ; MIPS64R6-NEXT: .LBB14_1: # %entry ; MIPS64R6-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS64R6-NEXT: ll $7, 0($3) +; MIPS64R6-NEXT: ll $7, 0($2) ; MIPS64R6-NEXT: addu $8, $7, $4 ; MIPS64R6-NEXT: and $8, $8, $5 ; MIPS64R6-NEXT: and $9, $7, $6 ; MIPS64R6-NEXT: or $9, $9, $8 -; MIPS64R6-NEXT: sc $9, 0($3) +; MIPS64R6-NEXT: sc $9, 0($2) ; MIPS64R6-NEXT: beqzc $9, .LBB14_1 ; MIPS64R6-NEXT: # %bb.2: # %entry -; MIPS64R6-NEXT: and $2, $7, $5 -; MIPS64R6-NEXT: srlv $2, $2, $1 -; MIPS64R6-NEXT: seh $2, $2 +; MIPS64R6-NEXT: and $1, $7, $5 +; MIPS64R6-NEXT: srlv $1, $1, $3 +; MIPS64R6-NEXT: seh $1, $1 ; MIPS64R6-NEXT: # %bb.3: # %entry -; MIPS64R6-NEXT: jrc $ra +; MIPS64R6-NEXT: jr $ra +; MIPS64R6-NEXT: seh $2, $1 ; ; MIPS64R6O0-LABEL: AtomicLoadAdd16: ; MIPS64R6O0: # %bb.0: # %entry @@ -5728,7 +5782,8 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS64R6O0-NEXT: # %bb.3: # %entry ; MIPS64R6O0-NEXT: sw $1, 12($sp) # 4-byte Folded Spill ; MIPS64R6O0-NEXT: # %bb.4: # %entry -; MIPS64R6O0-NEXT: lw $2, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: lw $1, 12($sp) # 4-byte Folded Reload +; MIPS64R6O0-NEXT: seh $2, $1 ; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16 ; MIPS64R6O0-NEXT: jrc $ra ; @@ -5739,28 +5794,29 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MM32-NEXT: addu $2, $2, $25 ; MM32-NEXT: lw $1, %got(z)($2) ; MM32-NEXT: addiu $2, $zero, -4 -; MM32-NEXT: and $3, $1, $2 +; MM32-NEXT: and $2, $1, $2 ; MM32-NEXT: andi $1, $1, 3 -; MM32-NEXT: sll $1, $1, 3 -; MM32-NEXT: ori $2, $zero, 65535 -; MM32-NEXT: sllv $5, $2, $1 +; MM32-NEXT: sll $3, $1, 3 +; MM32-NEXT: ori $1, $zero, 65535 +; MM32-NEXT: sllv $5, $1, $3 ; MM32-NEXT: nor $6, $zero, $5 -; MM32-NEXT: sllv $4, $4, $1 +; MM32-NEXT: sllv $4, $4, $3 ; MM32-NEXT: $BB14_1: # %entry ; MM32-NEXT: # =>This Inner Loop Header: Depth=1 -; MM32-NEXT: ll $7, 0($3) +; MM32-NEXT: ll $7, 0($2) ; MM32-NEXT: addu $8, $7, $4 ; MM32-NEXT: and $8, $8, $5 ; MM32-NEXT: and $9, $7, $6 ; MM32-NEXT: or $9, $9, $8 -; MM32-NEXT: sc $9, 0($3) +; MM32-NEXT: sc $9, 0($2) ; MM32-NEXT: beqzc $9, $BB14_1 ; MM32-NEXT: # %bb.2: # %entry -; MM32-NEXT: and $2, $7, $5 -; MM32-NEXT: srlv $2, $2, $1 -; MM32-NEXT: seh $2, $2 +; MM32-NEXT: and $1, $7, $5 +; MM32-NEXT: srlv $1, $1, $3 +; MM32-NEXT: seh $1, $1 ; MM32-NEXT: # %bb.3: # %entry -; MM32-NEXT: jrc $ra +; MM32-NEXT: jr $ra +; MM32-NEXT: seh $2, $1 ; ; O1-LABEL: AtomicLoadAdd16: ; O1: # %bb.0: # %entry @@ -5769,31 +5825,32 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; O1-NEXT: addu $1, $2, $25 ; O1-NEXT: lw $1, %got(z)($1) ; O1-NEXT: addiu $2, $zero, -4 -; O1-NEXT: and $3, $1, $2 +; O1-NEXT: and $2, $1, $2 ; O1-NEXT: andi $1, $1, 3 -; O1-NEXT: sll $1, $1, 3 -; O1-NEXT: ori $2, $zero, 65535 -; O1-NEXT: sllv $5, $2, $1 +; O1-NEXT: sll $3, $1, 3 +; O1-NEXT: ori $1, $zero, 65535 +; O1-NEXT: sllv $5, $1, $3 ; O1-NEXT: nor $6, $zero, $5 -; O1-NEXT: sllv $4, $4, $1 +; O1-NEXT: sllv $4, $4, $3 ; O1-NEXT: $BB14_1: # %entry ; O1-NEXT: # =>This Inner Loop Header: Depth=1 -; O1-NEXT: ll $7, 0($3) +; O1-NEXT: ll $7, 0($2) ; O1-NEXT: addu $8, $7, $4 ; O1-NEXT: and $8, $8, $5 ; O1-NEXT: and $9, $7, $6 ; O1-NEXT: or $9, $9, $8 -; O1-NEXT: sc $9, 0($3) +; O1-NEXT: sc $9, 0($2) ; O1-NEXT: beqz $9, $BB14_1 ; O1-NEXT: nop ; O1-NEXT: # %bb.2: # %entry -; O1-NEXT: and $2, $7, $5 -; O1-NEXT: srlv $2, $2, $1 -; O1-NEXT: sll $2, $2, 16 -; O1-NEXT: sra $2, $2, 16 +; O1-NEXT: and $1, $7, $5 +; O1-NEXT: srlv $1, $1, $3 +; O1-NEXT: sll $1, $1, 16 +; O1-NEXT: sra $1, $1, 16 ; O1-NEXT: # %bb.3: # %entry +; O1-NEXT: sll $1, $1, 16 ; O1-NEXT: jr $ra -; O1-NEXT: nop +; O1-NEXT: sra $2, $1, 16 ; ; O2-LABEL: AtomicLoadAdd16: ; O2: # %bb.0: # %entry @@ -5802,31 +5859,32 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; O2-NEXT: addu $1, $2, $25 ; O2-NEXT: lw $1, %got(z)($1) ; O2-NEXT: addiu $2, $zero, -4 -; O2-NEXT: and $3, $1, $2 +; O2-NEXT: and $2, $1, $2 ; O2-NEXT: andi $1, $1, 3 -; O2-NEXT: sll $1, $1, 3 -; O2-NEXT: ori $2, $zero, 65535 -; O2-NEXT: sllv $5, $2, $1 +; O2-NEXT: sll $3, $1, 3 +; O2-NEXT: ori $1, $zero, 65535 +; O2-NEXT: sllv $5, $1, $3 ; O2-NEXT: nor $6, $zero, $5 -; O2-NEXT: sllv $4, $4, $1 +; O2-NEXT: sllv $4, $4, $3 ; O2-NEXT: $BB14_1: # %entry ; O2-NEXT: # =>This Inner Loop Header: Depth=1 -; O2-NEXT: ll $7, 0($3) +; O2-NEXT: ll $7, 0($2) ; O2-NEXT: addu $8, $7, $4 ; O2-NEXT: and $8, $8, $5 ; O2-NEXT: and $9, $7, $6 ; O2-NEXT: or $9, $9, $8 -; O2-NEXT: sc $9, 0($3) +; O2-NEXT: sc $9, 0($2) ; O2-NEXT: beqz $9, $BB14_1 ; O2-NEXT: nop ; O2-NEXT: # %bb.2: # %entry -; O2-NEXT: and $2, $7, $5 -; O2-NEXT: srlv $2, $2, $1 -; O2-NEXT: sll $2, $2, 16 -; O2-NEXT: sra $2, $2, 16 +; O2-NEXT: and $1, $7, $5 +; O2-NEXT: srlv $1, $1, $3 +; O2-NEXT: sll $1, $1, 16 +; O2-NEXT: sra $1, $1, 16 ; O2-NEXT: # %bb.3: # %entry +; O2-NEXT: sll $1, $1, 16 ; O2-NEXT: jr $ra -; O2-NEXT: nop +; O2-NEXT: sra $2, $1, 16 ; ; O3-LABEL: AtomicLoadAdd16: ; O3: # %bb.0: # %entry @@ -5835,31 +5893,32 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; O3-NEXT: addu $1, $2, $25 ; O3-NEXT: addiu $2, $zero, -4 ; O3-NEXT: lw $1, %got(z)($1) -; O3-NEXT: and $3, $1, $2 +; O3-NEXT: and $2, $1, $2 ; O3-NEXT: andi $1, $1, 3 -; O3-NEXT: ori $2, $zero, 65535 -; O3-NEXT: sll $1, $1, 3 -; O3-NEXT: sllv $5, $2, $1 -; O3-NEXT: sllv $4, $4, $1 +; O3-NEXT: sll $3, $1, 3 +; O3-NEXT: ori $1, $zero, 65535 +; O3-NEXT: sllv $5, $1, $3 +; O3-NEXT: sllv $4, $4, $3 ; O3-NEXT: nor $6, $zero, $5 ; O3-NEXT: $BB14_1: # %entry ; O3-NEXT: # =>This Inner Loop Header: Depth=1 -; O3-NEXT: ll $7, 0($3) +; O3-NEXT: ll $7, 0($2) ; O3-NEXT: addu $8, $7, $4 ; O3-NEXT: and $8, $8, $5 ; O3-NEXT: and $9, $7, $6 ; O3-NEXT: or $9, $9, $8 -; O3-NEXT: sc $9, 0($3) +; O3-NEXT: sc $9, 0($2) ; O3-NEXT: beqz $9, $BB14_1 ; O3-NEXT: nop ; O3-NEXT: # %bb.2: # %entry -; O3-NEXT: and $2, $7, $5 -; O3-NEXT: srlv $2, $2, $1 -; O3-NEXT: sll $2, $2, 16 -; O3-NEXT: sra $2, $2, 16 +; O3-NEXT: and $1, $7, $5 +; O3-NEXT: srlv $1, $1, $3 +; O3-NEXT: sll $1, $1, 16 +; O3-NEXT: sra $1, $1, 16 ; O3-NEXT: # %bb.3: # %entry +; O3-NEXT: sll $1, $1, 16 ; O3-NEXT: jr $ra -; O3-NEXT: nop +; O3-NEXT: sra $2, $1, 16 ; ; MIPS32EB-LABEL: AtomicLoadAdd16: ; MIPS32EB: # %bb.0: # %entry @@ -5868,32 +5927,33 @@ define signext i16 @AtomicLoadAdd16(i16 signext %incr) nounwind { ; MIPS32EB-NEXT: addu $1, $2, $25 ; MIPS32EB-NEXT: lw $1, %got(z)($1) ; MIPS32EB-NEXT: addiu $2, $zero, -4 -; MIPS32EB-NEXT: and $3, $1, $2 +; MIPS32EB-NEXT: and $2, $1, $2 ; MIPS32EB-NEXT: andi $1, $1, 3 ; MIPS32EB-NEXT: xori $1, $1, 2 -; MIPS32EB-NEXT: sll $1, $1, 3 -; MIPS32EB-NEXT: ori $2, $zero, 65535 -; MIPS32EB-NEXT: sllv $5, $2, $1 +; MIPS32EB-NEXT: sll $3, $1, 3 +; MIPS32EB-NEXT: ori $1, $zero, 65535 +; MIPS32EB-NEXT: sllv $5, $1, $3 ; MIPS32EB-NEXT: nor $6, $zero, $5 -; MIPS32EB-NEXT: sllv $4, $4, $1 +; MIPS32EB-NEXT: sllv $4, $4, $3 ; MIPS32EB-NEXT: $BB14_1: # %entry ; MIPS32EB-NEXT: # =>This Inner Loop Header: Depth=1 -; MIPS32EB-NEXT: ll $7, 0($3) +; MIPS32EB-NEXT: ll $7, 0($2) ; MIPS32EB-NEXT: addu $8, $7, $4 ; MIPS32EB-NEXT: and $8, $8, $5 ; MIPS32EB-NEXT: and $9, $7, $6 ; MIPS32EB-NEXT: or $9, $9, $8 -; MIPS32EB-NEXT: sc $9, 0($3) +; MIPS32EB-NEXT: sc $9, 0($2) ; MIPS32EB-NEXT: beqz $9, $BB14_1 ; MIPS32EB-NEXT: nop ; MIPS32EB-NEXT: # %bb.2: # %entry -; MIPS32EB-NEXT: and $2, $7, $5 -; MIPS32EB-NEXT: srlv $2, $2, $1 -; MIPS32EB-NEXT: sll $2, $2, 16 -; MIPS32EB-NEXT: sra $2, $2, 16 +; MIPS32EB-NEXT: and $1, $7, $5 +; MIPS32EB-NEXT: srlv $1, $1, $3 +; MIPS32EB-NEXT: sll $1, $1, 16 +; MIPS32EB-NEXT: sra $1, $1, 16 ; MIPS32EB-NEXT: # %bb.3: # %entry +; MIPS32EB-NEXT: sll $1, $1, 16 ; MIPS32EB-NEXT: jr $ra -; MIPS32EB-NEXT: nop +; MIPS32EB-NEXT: sra $2, $1, 16 entry: %0 = atomicrmw add i16* @z, i16 %incr monotonic ret i16 %0 diff --git a/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll index d7dfc56253c7..2aa8ea3eff34 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-i16-ldst.ll @@ -23,7 +23,7 @@ define dso_local signext i16 @ld_0_int16_t_uint8_t(i64 %ptr) { ; CHECK-LABEL: ld_0_int16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i8* @@ -37,7 +37,7 @@ define dso_local signext i16 @ld_align16_int16_t_uint8_t(i8* nocapture readonly ; CHECK-LABEL: ld_align16_int16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -52,7 +52,7 @@ define dso_local signext i16 @ld_align32_int16_t_uint8_t(i8* nocapture readonly ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_int16_t_uint8_t: @@ -60,7 +60,7 @@ define dso_local signext i16 @ld_align32_int16_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -76,7 +76,7 @@ define dso_local signext i16 @ld_align64_int16_t_uint8_t(i8* nocapture readonly ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_int16_t_uint8_t: @@ -85,7 +85,7 @@ define dso_local signext i16 @ld_align64_int16_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -99,7 +99,7 @@ define dso_local signext i16 @ld_reg_int16_t_uint8_t(i8* nocapture readonly %ptr ; CHECK-LABEL: ld_reg_int16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -114,7 +114,7 @@ define dso_local signext i16 @ld_or_int16_t_uint8_t(i64 %ptr, i8 zeroext %off) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -131,7 +131,7 @@ define dso_local signext i16 @ld_not_disjoint16_int16_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -147,7 +147,7 @@ define dso_local signext i16 @ld_disjoint_align16_int16_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lbz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -165,7 +165,7 @@ define dso_local signext i16 @ld_not_disjoint32_int16_t_uint8_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -183,7 +183,7 @@ define dso_local signext i16 @ld_disjoint_align32_int16_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_int16_t_uint8_t: @@ -193,7 +193,7 @@ define dso_local signext i16 @ld_disjoint_align32_int16_t_uint8_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lbzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_int16_t_uint8_t: @@ -203,7 +203,7 @@ define dso_local signext i16 @ld_disjoint_align32_int16_t_uint8_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lbzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 56 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -223,7 +223,7 @@ define dso_local signext i16 @ld_not_disjoint64_int16_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_int16_t_uint8_t: @@ -234,7 +234,7 @@ define dso_local signext i16 @ld_not_disjoint64_int16_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -252,7 +252,7 @@ define dso_local signext i16 @ld_disjoint_align64_int16_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_int16_t_uint8_t: @@ -262,7 +262,7 @@ define dso_local signext i16 @ld_disjoint_align64_int16_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -278,7 +278,7 @@ define dso_local signext i16 @ld_cst_align16_int16_t_uint8_t() { ; CHECK-LABEL: ld_cst_align16_int16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16 @@ -292,7 +292,7 @@ define dso_local signext i16 @ld_cst_align32_int16_t_uint8_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lbz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4 @@ -307,7 +307,7 @@ define dso_local signext i16 @ld_cst_align64_int16_t_uint8_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_int16_t_uint8_t: @@ -316,7 +316,7 @@ define dso_local signext i16 @ld_cst_align64_int16_t_uint8_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096 @@ -1550,7 +1550,7 @@ define dso_local zeroext i16 @ld_0_uint16_t_uint8_t(i64 %ptr) { ; CHECK-LABEL: ld_0_uint16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i8* @@ -1564,7 +1564,7 @@ define dso_local zeroext i16 @ld_align16_uint16_t_uint8_t(i8* nocapture readonly ; CHECK-LABEL: ld_align16_uint16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -1579,7 +1579,7 @@ define dso_local zeroext i16 @ld_align32_uint16_t_uint8_t(i8* nocapture readonly ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_uint16_t_uint8_t: @@ -1587,7 +1587,7 @@ define dso_local zeroext i16 @ld_align32_uint16_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -1603,7 +1603,7 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint8_t(i8* nocapture readonly ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint8_t: @@ -1612,7 +1612,7 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -1626,7 +1626,7 @@ define dso_local zeroext i16 @ld_reg_uint16_t_uint8_t(i8* nocapture readonly %pt ; CHECK-LABEL: ld_reg_uint16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -1641,7 +1641,7 @@ define dso_local zeroext i16 @ld_or_uint16_t_uint8_t(i64 %ptr, i8 zeroext %off) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -1658,7 +1658,7 @@ define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -1674,7 +1674,7 @@ define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lbz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -1692,7 +1692,7 @@ define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint8_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -1710,7 +1710,7 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint8_t: @@ -1720,7 +1720,7 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint8_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lbzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint8_t: @@ -1730,7 +1730,7 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint8_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lbzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 56 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -1750,7 +1750,7 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint8_t: @@ -1761,7 +1761,7 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -1779,7 +1779,7 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint8_t: @@ -1789,7 +1789,7 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -1805,7 +1805,7 @@ define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint8_t() { ; CHECK-LABEL: ld_cst_align16_uint16_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16 @@ -1819,7 +1819,7 @@ define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint8_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lbz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4 @@ -1834,7 +1834,7 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint8_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint8_t: @@ -1843,7 +1843,7 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint8_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096 @@ -2184,7 +2184,7 @@ define dso_local zeroext i16 @ld_0_uint16_t_uint16_t(i64 %ptr) { ; CHECK-LABEL: ld_0_uint16_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i16* @@ -2197,7 +2197,7 @@ define dso_local zeroext i16 @ld_align16_uint16_t_uint16_t(i8* nocapture readonl ; CHECK-LABEL: ld_align16_uint16_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -2212,7 +2212,7 @@ define dso_local zeroext i16 @ld_align32_uint16_t_uint16_t(i8* nocapture readonl ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_uint16_t_uint16_t: @@ -2220,7 +2220,7 @@ define dso_local zeroext i16 @ld_align32_uint16_t_uint16_t(i8* nocapture readonl ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -2236,7 +2236,7 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint16_t(i8* nocapture readonl ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_uint16_t_uint16_t: @@ -2245,7 +2245,7 @@ define dso_local zeroext i16 @ld_align64_uint16_t_uint16_t(i8* nocapture readonl ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -2259,7 +2259,7 @@ define dso_local zeroext i16 @ld_reg_uint16_t_uint16_t(i8* nocapture readonly %p ; CHECK-LABEL: ld_reg_uint16_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -2274,7 +2274,7 @@ define dso_local zeroext i16 @ld_or_uint16_t_uint16_t(i64 %ptr, i8 zeroext %off) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -2290,7 +2290,7 @@ define dso_local zeroext i16 @ld_not_disjoint16_uint16_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -2305,7 +2305,7 @@ define dso_local zeroext i16 @ld_disjoint_align16_uint16_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lhz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -2322,7 +2322,7 @@ define dso_local zeroext i16 @ld_not_disjoint32_uint16_t_uint16_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -2339,7 +2339,7 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_uint16_t_uint16_t: @@ -2349,7 +2349,7 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint16_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lhzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_uint16_t_uint16_t: @@ -2359,7 +2359,7 @@ define dso_local zeroext i16 @ld_disjoint_align32_uint16_t_uint16_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lhzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -2378,7 +2378,7 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint16_t_uint16_t: @@ -2389,7 +2389,7 @@ define dso_local zeroext i16 @ld_not_disjoint64_uint16_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -2406,7 +2406,7 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint16_t_uint16_t: @@ -2416,7 +2416,7 @@ define dso_local zeroext i16 @ld_disjoint_align64_uint16_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -2431,7 +2431,7 @@ define dso_local zeroext i16 @ld_cst_align16_uint16_t_uint16_t() { ; CHECK-LABEL: ld_cst_align16_uint16_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16 @@ -2444,7 +2444,7 @@ define dso_local zeroext i16 @ld_cst_align32_uint16_t_uint16_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lhz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4 @@ -2458,7 +2458,7 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint16_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_uint16_t_uint16_t: @@ -2467,7 +2467,7 @@ define dso_local zeroext i16 @ld_cst_align64_uint16_t_uint16_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096 diff --git a/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll index 2b86dd79c9ec..a1097bcdcdfb 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-i32-ldst.ll @@ -23,7 +23,7 @@ define dso_local signext i32 @ld_0_int32_t_uint8_t(i64 %ptr) { ; CHECK-LABEL: ld_0_int32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i8* @@ -37,7 +37,7 @@ define dso_local signext i32 @ld_align16_int32_t_uint8_t(i8* nocapture readonly ; CHECK-LABEL: ld_align16_int32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -52,7 +52,7 @@ define dso_local signext i32 @ld_align32_int32_t_uint8_t(i8* nocapture readonly ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_int32_t_uint8_t: @@ -60,7 +60,7 @@ define dso_local signext i32 @ld_align32_int32_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -76,7 +76,7 @@ define dso_local signext i32 @ld_align64_int32_t_uint8_t(i8* nocapture readonly ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint8_t: @@ -85,7 +85,7 @@ define dso_local signext i32 @ld_align64_int32_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -99,7 +99,7 @@ define dso_local signext i32 @ld_reg_int32_t_uint8_t(i8* nocapture readonly %ptr ; CHECK-LABEL: ld_reg_int32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -114,7 +114,7 @@ define dso_local signext i32 @ld_or_int32_t_uint8_t(i64 %ptr, i8 zeroext %off) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -131,7 +131,7 @@ define dso_local signext i32 @ld_not_disjoint16_int32_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -147,7 +147,7 @@ define dso_local signext i32 @ld_disjoint_align16_int32_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lbz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -165,7 +165,7 @@ define dso_local signext i32 @ld_not_disjoint32_int32_t_uint8_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -183,7 +183,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint8_t: @@ -193,7 +193,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint8_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lbzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint8_t: @@ -203,7 +203,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint8_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lbzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 56 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -223,7 +223,7 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint8_t: @@ -234,7 +234,7 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -252,7 +252,7 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint8_t: @@ -262,7 +262,7 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -278,7 +278,7 @@ define dso_local signext i32 @ld_cst_align16_int32_t_uint8_t() { ; CHECK-LABEL: ld_cst_align16_int32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16 @@ -292,7 +292,7 @@ define dso_local signext i32 @ld_cst_align32_int32_t_uint8_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lbz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4 @@ -307,7 +307,7 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint8_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint8_t: @@ -316,7 +316,7 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint8_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096 @@ -635,7 +635,7 @@ define dso_local signext i32 @ld_0_int32_t_uint16_t(i64 %ptr) { ; CHECK-LABEL: ld_0_int32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i16* @@ -649,7 +649,7 @@ define dso_local signext i32 @ld_align16_int32_t_uint16_t(i8* nocapture readonly ; CHECK-LABEL: ld_align16_int32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -665,7 +665,7 @@ define dso_local signext i32 @ld_align32_int32_t_uint16_t(i8* nocapture readonly ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_int32_t_uint16_t: @@ -673,7 +673,7 @@ define dso_local signext i32 @ld_align32_int32_t_uint16_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -690,7 +690,7 @@ define dso_local signext i32 @ld_align64_int32_t_uint16_t(i8* nocapture readonly ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_int32_t_uint16_t: @@ -699,7 +699,7 @@ define dso_local signext i32 @ld_align64_int32_t_uint16_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -714,7 +714,7 @@ define dso_local signext i32 @ld_reg_int32_t_uint16_t(i8* nocapture readonly %pt ; CHECK-LABEL: ld_reg_int32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -730,7 +730,7 @@ define dso_local signext i32 @ld_or_int32_t_uint16_t(i64 %ptr, i8 zeroext %off) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -747,7 +747,7 @@ define dso_local signext i32 @ld_not_disjoint16_int32_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -763,7 +763,7 @@ define dso_local signext i32 @ld_disjoint_align16_int32_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lhz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -781,7 +781,7 @@ define dso_local signext i32 @ld_not_disjoint32_int32_t_uint16_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -799,7 +799,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_int32_t_uint16_t: @@ -809,7 +809,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint16_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lhzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_int32_t_uint16_t: @@ -819,7 +819,7 @@ define dso_local signext i32 @ld_disjoint_align32_int32_t_uint16_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lhzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -839,7 +839,7 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_int32_t_uint16_t: @@ -850,7 +850,7 @@ define dso_local signext i32 @ld_not_disjoint64_int32_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -868,7 +868,7 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_int32_t_uint16_t: @@ -878,7 +878,7 @@ define dso_local signext i32 @ld_disjoint_align64_int32_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -894,7 +894,7 @@ define dso_local signext i32 @ld_cst_align16_int32_t_uint16_t() { ; CHECK-LABEL: ld_cst_align16_int32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16 @@ -908,7 +908,7 @@ define dso_local signext i32 @ld_cst_align32_int32_t_uint16_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lhz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4 @@ -923,7 +923,7 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint16_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_int32_t_uint16_t: @@ -932,7 +932,7 @@ define dso_local signext i32 @ld_cst_align64_int32_t_uint16_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096 @@ -1860,7 +1860,7 @@ define dso_local zeroext i32 @ld_0_uint32_t_uint8_t(i64 %ptr) { ; CHECK-LABEL: ld_0_uint32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i8* @@ -1874,7 +1874,7 @@ define dso_local zeroext i32 @ld_align16_uint32_t_uint8_t(i8* nocapture readonly ; CHECK-LABEL: ld_align16_uint32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -1889,7 +1889,7 @@ define dso_local zeroext i32 @ld_align32_uint32_t_uint8_t(i8* nocapture readonly ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_uint32_t_uint8_t: @@ -1897,7 +1897,7 @@ define dso_local zeroext i32 @ld_align32_uint32_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -1913,7 +1913,7 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint8_t(i8* nocapture readonly ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint8_t: @@ -1922,7 +1922,7 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint8_t(i8* nocapture readonly ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -1936,7 +1936,7 @@ define dso_local zeroext i32 @ld_reg_uint32_t_uint8_t(i8* nocapture readonly %pt ; CHECK-LABEL: ld_reg_uint32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -1951,7 +1951,7 @@ define dso_local zeroext i32 @ld_or_uint32_t_uint8_t(i64 %ptr, i8 zeroext %off) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -1968,7 +1968,7 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -1984,7 +1984,7 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lbz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -2002,7 +2002,7 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint8_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -2020,7 +2020,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint8_t: @@ -2030,7 +2030,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint8_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lbzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint8_t: @@ -2040,7 +2040,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint8_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lbzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 56 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -2060,7 +2060,7 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint8_t: @@ -2071,7 +2071,7 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -2089,7 +2089,7 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint8_t: @@ -2099,7 +2099,7 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -2115,7 +2115,7 @@ define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint8_t() { ; CHECK-LABEL: ld_cst_align16_uint32_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16 @@ -2129,7 +2129,7 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint8_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lbz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4 @@ -2144,7 +2144,7 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint8_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint8_t: @@ -2153,7 +2153,7 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint8_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096 @@ -2494,7 +2494,7 @@ define dso_local zeroext i32 @ld_0_uint32_t_uint16_t(i64 %ptr) { ; CHECK-LABEL: ld_0_uint32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i16* @@ -2508,7 +2508,7 @@ define dso_local zeroext i32 @ld_align16_uint32_t_uint16_t(i8* nocapture readonl ; CHECK-LABEL: ld_align16_uint32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -2524,7 +2524,7 @@ define dso_local zeroext i32 @ld_align32_uint32_t_uint16_t(i8* nocapture readonl ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_uint32_t_uint16_t: @@ -2532,7 +2532,7 @@ define dso_local zeroext i32 @ld_align32_uint32_t_uint16_t(i8* nocapture readonl ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -2549,7 +2549,7 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint16_t(i8* nocapture readonl ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_uint32_t_uint16_t: @@ -2558,7 +2558,7 @@ define dso_local zeroext i32 @ld_align64_uint32_t_uint16_t(i8* nocapture readonl ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -2573,7 +2573,7 @@ define dso_local zeroext i32 @ld_reg_uint32_t_uint16_t(i8* nocapture readonly %p ; CHECK-LABEL: ld_reg_uint32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -2589,7 +2589,7 @@ define dso_local zeroext i32 @ld_or_uint32_t_uint16_t(i64 %ptr, i8 zeroext %off) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -2606,7 +2606,7 @@ define dso_local zeroext i32 @ld_not_disjoint16_uint32_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -2622,7 +2622,7 @@ define dso_local zeroext i32 @ld_disjoint_align16_uint32_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lhz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -2640,7 +2640,7 @@ define dso_local zeroext i32 @ld_not_disjoint32_uint32_t_uint16_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -2658,7 +2658,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_uint32_t_uint16_t: @@ -2668,7 +2668,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint16_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lhzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_uint32_t_uint16_t: @@ -2678,7 +2678,7 @@ define dso_local zeroext i32 @ld_disjoint_align32_uint32_t_uint16_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lhzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -2698,7 +2698,7 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint32_t_uint16_t: @@ -2709,7 +2709,7 @@ define dso_local zeroext i32 @ld_not_disjoint64_uint32_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -2727,7 +2727,7 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint32_t_uint16_t: @@ -2737,7 +2737,7 @@ define dso_local zeroext i32 @ld_disjoint_align64_uint32_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -2753,7 +2753,7 @@ define dso_local zeroext i32 @ld_cst_align16_uint32_t_uint16_t() { ; CHECK-LABEL: ld_cst_align16_uint32_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16 @@ -2767,7 +2767,7 @@ define dso_local zeroext i32 @ld_cst_align32_uint32_t_uint16_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lhz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4 @@ -2782,7 +2782,7 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint16_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_uint32_t_uint16_t: @@ -2791,7 +2791,7 @@ define dso_local zeroext i32 @ld_cst_align64_uint32_t_uint16_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096 diff --git a/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll index a8f505c2973a..ec4cb4c2e330 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-i64-ldst.ll @@ -23,7 +23,7 @@ define dso_local i64 @ld_0_int64_t_uint8_t(i64 %ptr) { ; CHECK-LABEL: ld_0_int64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i8* @@ -37,7 +37,7 @@ define dso_local i64 @ld_align16_int64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-LABEL: ld_align16_int64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -52,7 +52,7 @@ define dso_local i64 @ld_align32_int64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_int64_t_uint8_t: @@ -60,7 +60,7 @@ define dso_local i64 @ld_align32_int64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -76,7 +76,7 @@ define dso_local i64 @ld_align64_int64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint8_t: @@ -85,7 +85,7 @@ define dso_local i64 @ld_align64_int64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -99,7 +99,7 @@ define dso_local i64 @ld_reg_int64_t_uint8_t(i8* nocapture readonly %ptr, i64 %o ; CHECK-LABEL: ld_reg_int64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -114,7 +114,7 @@ define dso_local i64 @ld_or_int64_t_uint8_t(i64 %ptr, i8 zeroext %off) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -131,7 +131,7 @@ define dso_local i64 @ld_not_disjoint16_int64_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -147,7 +147,7 @@ define dso_local i64 @ld_disjoint_align16_int64_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lbz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -165,7 +165,7 @@ define dso_local i64 @ld_not_disjoint32_int64_t_uint8_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -183,7 +183,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_uint8_t: @@ -193,7 +193,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint8_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lbzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint8_t: @@ -203,7 +203,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint8_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lbzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 56 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -223,7 +223,7 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint8_t: @@ -234,7 +234,7 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -252,7 +252,7 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint8_t: @@ -262,7 +262,7 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -278,7 +278,7 @@ define dso_local i64 @ld_cst_align16_int64_t_uint8_t() { ; CHECK-LABEL: ld_cst_align16_int64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16 @@ -292,7 +292,7 @@ define dso_local i64 @ld_cst_align32_int64_t_uint8_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lbz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4 @@ -307,7 +307,7 @@ define dso_local i64 @ld_cst_align64_int64_t_uint8_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint8_t: @@ -316,7 +316,7 @@ define dso_local i64 @ld_cst_align64_int64_t_uint8_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096 @@ -635,7 +635,7 @@ define dso_local i64 @ld_0_int64_t_uint16_t(i64 %ptr) { ; CHECK-LABEL: ld_0_int64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i16* @@ -649,7 +649,7 @@ define dso_local i64 @ld_align16_int64_t_uint16_t(i8* nocapture readonly %ptr) { ; CHECK-LABEL: ld_align16_int64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -665,7 +665,7 @@ define dso_local i64 @ld_align32_int64_t_uint16_t(i8* nocapture readonly %ptr) { ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_int64_t_uint16_t: @@ -673,7 +673,7 @@ define dso_local i64 @ld_align32_int64_t_uint16_t(i8* nocapture readonly %ptr) { ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -690,7 +690,7 @@ define dso_local i64 @ld_align64_int64_t_uint16_t(i8* nocapture readonly %ptr) { ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_int64_t_uint16_t: @@ -699,7 +699,7 @@ define dso_local i64 @ld_align64_int64_t_uint16_t(i8* nocapture readonly %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -714,7 +714,7 @@ define dso_local i64 @ld_reg_int64_t_uint16_t(i8* nocapture readonly %ptr, i64 % ; CHECK-LABEL: ld_reg_int64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -730,7 +730,7 @@ define dso_local i64 @ld_or_int64_t_uint16_t(i64 %ptr, i8 zeroext %off) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -747,7 +747,7 @@ define dso_local i64 @ld_not_disjoint16_int64_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -763,7 +763,7 @@ define dso_local i64 @ld_disjoint_align16_int64_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lhz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -781,7 +781,7 @@ define dso_local i64 @ld_not_disjoint32_int64_t_uint16_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -799,7 +799,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_int64_t_uint16_t: @@ -809,7 +809,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint16_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lhzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_int64_t_uint16_t: @@ -819,7 +819,7 @@ define dso_local i64 @ld_disjoint_align32_int64_t_uint16_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lhzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -839,7 +839,7 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_int64_t_uint16_t: @@ -850,7 +850,7 @@ define dso_local i64 @ld_not_disjoint64_int64_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -868,7 +868,7 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_int64_t_uint16_t: @@ -878,7 +878,7 @@ define dso_local i64 @ld_disjoint_align64_int64_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -894,7 +894,7 @@ define dso_local i64 @ld_cst_align16_int64_t_uint16_t() { ; CHECK-LABEL: ld_cst_align16_int64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16 @@ -908,7 +908,7 @@ define dso_local i64 @ld_cst_align32_int64_t_uint16_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lhz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4 @@ -923,7 +923,7 @@ define dso_local i64 @ld_cst_align64_int64_t_uint16_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_int64_t_uint16_t: @@ -932,7 +932,7 @@ define dso_local i64 @ld_cst_align64_int64_t_uint16_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096 @@ -2148,7 +2148,7 @@ define dso_local i64 @ld_0_uint64_t_uint8_t(i64 %ptr) { ; CHECK-LABEL: ld_0_uint64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i8* @@ -2162,7 +2162,7 @@ define dso_local i64 @ld_align16_uint64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-LABEL: ld_align16_uint64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -2177,7 +2177,7 @@ define dso_local i64 @ld_align32_uint64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_uint64_t_uint8_t: @@ -2185,7 +2185,7 @@ define dso_local i64 @ld_align32_uint64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -2201,7 +2201,7 @@ define dso_local i64 @ld_align64_uint64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint8_t: @@ -2210,7 +2210,7 @@ define dso_local i64 @ld_align64_uint64_t_uint8_t(i8* nocapture readonly %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -2224,7 +2224,7 @@ define dso_local i64 @ld_reg_uint64_t_uint8_t(i8* nocapture readonly %ptr, i64 % ; CHECK-LABEL: ld_reg_uint64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -2239,7 +2239,7 @@ define dso_local i64 @ld_or_uint64_t_uint8_t(i64 %ptr, i8 zeroext %off) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -2256,7 +2256,7 @@ define dso_local i64 @ld_not_disjoint16_uint64_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -2272,7 +2272,7 @@ define dso_local i64 @ld_disjoint_align16_uint64_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lbz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -2290,7 +2290,7 @@ define dso_local i64 @ld_not_disjoint32_uint64_t_uint8_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -2308,7 +2308,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_uint8_t: @@ -2318,7 +2318,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint8_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lbzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint8_t: @@ -2328,7 +2328,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint8_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lbzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 56 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -2348,7 +2348,7 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint8_t: @@ -2359,7 +2359,7 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -2377,7 +2377,7 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint8_t: @@ -2387,7 +2387,7 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -2403,7 +2403,7 @@ define dso_local i64 @ld_cst_align16_uint64_t_uint8_t() { ; CHECK-LABEL: ld_cst_align16_uint64_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16 @@ -2417,7 +2417,7 @@ define dso_local i64 @ld_cst_align32_uint64_t_uint8_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lbz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4 @@ -2432,7 +2432,7 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint8_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint8_t: @@ -2441,7 +2441,7 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint8_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096 @@ -2760,7 +2760,7 @@ define dso_local i64 @ld_0_uint64_t_uint16_t(i64 %ptr) { ; CHECK-LABEL: ld_0_uint64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i16* @@ -2774,7 +2774,7 @@ define dso_local i64 @ld_align16_uint64_t_uint16_t(i8* nocapture readonly %ptr) ; CHECK-LABEL: ld_align16_uint64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -2790,7 +2790,7 @@ define dso_local i64 @ld_align32_uint64_t_uint16_t(i8* nocapture readonly %ptr) ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_uint64_t_uint16_t: @@ -2798,7 +2798,7 @@ define dso_local i64 @ld_align32_uint64_t_uint16_t(i8* nocapture readonly %ptr) ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -2815,7 +2815,7 @@ define dso_local i64 @ld_align64_uint64_t_uint16_t(i8* nocapture readonly %ptr) ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_uint64_t_uint16_t: @@ -2824,7 +2824,7 @@ define dso_local i64 @ld_align64_uint64_t_uint16_t(i8* nocapture readonly %ptr) ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -2839,7 +2839,7 @@ define dso_local i64 @ld_reg_uint64_t_uint16_t(i8* nocapture readonly %ptr, i64 ; CHECK-LABEL: ld_reg_uint64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -2855,7 +2855,7 @@ define dso_local i64 @ld_or_uint64_t_uint16_t(i64 %ptr, i8 zeroext %off) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -2872,7 +2872,7 @@ define dso_local i64 @ld_not_disjoint16_uint64_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -2888,7 +2888,7 @@ define dso_local i64 @ld_disjoint_align16_uint64_t_uint16_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lhz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -2906,7 +2906,7 @@ define dso_local i64 @ld_not_disjoint32_uint64_t_uint16_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lhz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -2924,7 +2924,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_uint64_t_uint16_t: @@ -2934,7 +2934,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint16_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lhzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 48 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_uint64_t_uint16_t: @@ -2944,7 +2944,7 @@ define dso_local i64 @ld_disjoint_align32_uint64_t_uint16_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lhzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -2964,7 +2964,7 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint64_t_uint16_t: @@ -2975,7 +2975,7 @@ define dso_local i64 @ld_not_disjoint64_uint64_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -2993,7 +2993,7 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint16_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lhzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint64_t_uint16_t: @@ -3003,7 +3003,7 @@ define dso_local i64 @ld_disjoint_align64_uint64_t_uint16_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lhzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -3019,7 +3019,7 @@ define dso_local i64 @ld_cst_align16_uint64_t_uint16_t() { ; CHECK-LABEL: ld_cst_align16_uint64_t_uint16_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lhz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 4080 to i16*) monotonic, align 16 @@ -3033,7 +3033,7 @@ define dso_local i64 @ld_cst_align32_uint64_t_uint16_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lhz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 48 ; CHECK-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 9999900 to i16*) monotonic, align 4 @@ -3048,7 +3048,7 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint16_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lhz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 48 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_uint64_t_uint16_t: @@ -3057,7 +3057,7 @@ define dso_local i64 @ld_cst_align64_uint64_t_uint16_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lhz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 48 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i16, i16* inttoptr (i64 1000000000000 to i16*) monotonic, align 4096 diff --git a/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll b/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll index ad13b5b5211f..1d202c784aa2 100644 --- a/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll +++ b/llvm/test/CodeGen/PowerPC/atomics-i8-ldst.ll @@ -1244,7 +1244,7 @@ define dso_local zeroext i8 @ld_0_uint8_t_uint8_t(i64 %ptr) { ; CHECK-LABEL: ld_0_uint8_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = inttoptr i64 %ptr to i8* @@ -1257,7 +1257,7 @@ define dso_local zeroext i8 @ld_align16_uint8_t_uint8_t(i8* nocapture readonly % ; CHECK-LABEL: ld_align16_uint8_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 8(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 8 @@ -1271,7 +1271,7 @@ define dso_local zeroext i8 @ld_align32_uint8_t_uint8_t(i8* nocapture readonly % ; CHECK-P10: # %bb.0: # %entry ; CHECK-P10-NEXT: pli r4, 99999000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align32_uint8_t_uint8_t: @@ -1279,7 +1279,7 @@ define dso_local zeroext i8 @ld_align32_uint8_t_uint8_t(i8* nocapture readonly % ; CHECK-PREP10-NEXT: lis r4, 1525 ; CHECK-PREP10-NEXT: ori r4, r4, 56600 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 99999000 @@ -1294,7 +1294,7 @@ define dso_local zeroext i8 @ld_align64_uint8_t_uint8_t(i8* nocapture readonly % ; CHECK-P10-NEXT: pli r4, 244140625 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_align64_uint8_t_uint8_t: @@ -1303,7 +1303,7 @@ define dso_local zeroext i8 @ld_align64_uint8_t_uint8_t(i8* nocapture readonly % ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 1000000000000 @@ -1316,7 +1316,7 @@ define dso_local zeroext i8 @ld_reg_uint8_t_uint8_t(i8* nocapture readonly %ptr, ; CHECK-LABEL: ld_reg_uint8_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbzx r3, r3, r4 -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %add.ptr = getelementptr inbounds i8, i8* %ptr, i64 %off @@ -1330,7 +1330,7 @@ define dso_local zeroext i8 @ld_or_uint8_t_uint8_t(i64 %ptr, i8 zeroext %off) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %conv = zext i8 %off to i64 @@ -1346,7 +1346,7 @@ define dso_local zeroext i8 @ld_not_disjoint16_uint8_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ori r3, r3, 6 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 6 @@ -1361,7 +1361,7 @@ define dso_local zeroext i8 @ld_disjoint_align16_uint8_t_uint8_t(i64 %ptr) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: rldicr r3, r3, 0, 51 ; CHECK-NEXT: lbz r3, 24(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %and = and i64 %ptr, -4096 @@ -1378,7 +1378,7 @@ define dso_local zeroext i8 @ld_not_disjoint32_uint8_t_uint8_t(i64 %ptr) { ; CHECK-NEXT: ori r3, r3, 34463 ; CHECK-NEXT: oris r3, r3, 1 ; CHECK-NEXT: lbz r3, 0(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %or = or i64 %ptr, 99999 @@ -1395,7 +1395,7 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: and r3, r3, r4 ; CHECK-P10-NEXT: pli r4, 999990000 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-P9-LABEL: ld_disjoint_align32_uint8_t_uint8_t: @@ -1405,7 +1405,7 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_uint8_t(i64 %ptr) { ; CHECK-P9-NEXT: lis r4, 15258 ; CHECK-P9-NEXT: ori r4, r4, 41712 ; CHECK-P9-NEXT: lbzx r3, r3, r4 -; CHECK-P9-NEXT: clrldi r3, r3, 32 +; CHECK-P9-NEXT: clrldi r3, r3, 56 ; CHECK-P9-NEXT: blr ; ; CHECK-P8-LABEL: ld_disjoint_align32_uint8_t_uint8_t: @@ -1415,7 +1415,7 @@ define dso_local zeroext i8 @ld_disjoint_align32_uint8_t_uint8_t(i64 %ptr) { ; CHECK-P8-NEXT: and r3, r3, r4 ; CHECK-P8-NEXT: ori r4, r5, 41712 ; CHECK-P8-NEXT: lbzx r3, r3, r4 -; CHECK-P8-NEXT: clrldi r3, r3, 32 +; CHECK-P8-NEXT: clrldi r3, r3, 56 ; CHECK-P8-NEXT: blr entry: %and = and i64 %ptr, -1000341504 @@ -1434,7 +1434,7 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldimi r5, r4, 32, 0 ; CHECK-P10-NEXT: or r3, r3, r5 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_not_disjoint64_uint8_t_uint8_t: @@ -1445,7 +1445,7 @@ define dso_local zeroext i8 @ld_not_disjoint64_uint8_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 4097 ; CHECK-PREP10-NEXT: or r3, r3, r4 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %or = or i64 %ptr, 1000000000001 @@ -1462,7 +1462,7 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_uint8_t(i64 %ptr) { ; CHECK-P10-NEXT: rldicr r3, r3, 0, 23 ; CHECK-P10-NEXT: rldic r4, r4, 12, 24 ; CHECK-P10-NEXT: lbzx r3, r3, r4 -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_disjoint_align64_uint8_t_uint8_t: @@ -1472,7 +1472,7 @@ define dso_local zeroext i8 @ld_disjoint_align64_uint8_t_uint8_t(i64 %ptr) { ; CHECK-PREP10-NEXT: ori r4, r4, 19025 ; CHECK-PREP10-NEXT: rldic r4, r4, 12, 24 ; CHECK-PREP10-NEXT: lbzx r3, r3, r4 -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %and = and i64 %ptr, -1099511627776 @@ -1487,7 +1487,7 @@ define dso_local zeroext i8 @ld_cst_align16_uint8_t_uint8_t() { ; CHECK-LABEL: ld_cst_align16_uint8_t_uint8_t: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lbz r3, 4080(0) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 4080 to i8*) monotonic, align 16 @@ -1500,7 +1500,7 @@ define dso_local zeroext i8 @ld_cst_align32_uint8_t_uint8_t() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lis r3, 153 ; CHECK-NEXT: lbz r3, -27108(r3) -; CHECK-NEXT: clrldi r3, r3, 32 +; CHECK-NEXT: clrldi r3, r3, 56 ; CHECK-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 9999900 to i8*) monotonic, align 4 @@ -1514,7 +1514,7 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_uint8_t() { ; CHECK-P10-NEXT: pli r3, 244140625 ; CHECK-P10-NEXT: rldic r3, r3, 12, 24 ; CHECK-P10-NEXT: lbz r3, 0(r3) -; CHECK-P10-NEXT: clrldi r3, r3, 32 +; CHECK-P10-NEXT: clrldi r3, r3, 56 ; CHECK-P10-NEXT: blr ; ; CHECK-PREP10-LABEL: ld_cst_align64_uint8_t_uint8_t: @@ -1523,7 +1523,7 @@ define dso_local zeroext i8 @ld_cst_align64_uint8_t_uint8_t() { ; CHECK-PREP10-NEXT: ori r3, r3, 19025 ; CHECK-PREP10-NEXT: rldic r3, r3, 12, 24 ; CHECK-PREP10-NEXT: lbz r3, 0(r3) -; CHECK-PREP10-NEXT: clrldi r3, r3, 32 +; CHECK-PREP10-NEXT: clrldi r3, r3, 56 ; CHECK-PREP10-NEXT: blr entry: %0 = load atomic i8, i8* inttoptr (i64 1000000000000 to i8*) monotonic, align 4096 diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll index dee847c7cdae..767757ad5716 100644 --- a/llvm/test/CodeGen/RISCV/atomic-signext.ll +++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -24,6 +24,8 @@ define signext i8 @atomic_load_i8_unordered(i8 *%a) nounwind { ; RV32IA-LABEL: atomic_load_i8_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lb a0, 0(a0) +; RV32IA-NEXT: slli a0, a0, 24 +; RV32IA-NEXT: srai a0, a0, 24 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomic_load_i8_unordered: @@ -41,6 +43,8 @@ define signext i8 @atomic_load_i8_unordered(i8 *%a) nounwind { ; RV64IA-LABEL: atomic_load_i8_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lb a0, 0(a0) +; RV64IA-NEXT: slli a0, a0, 56 +; RV64IA-NEXT: srai a0, a0, 56 ; RV64IA-NEXT: ret %1 = load atomic i8, i8* %a unordered, align 1 ret i8 %1 @@ -62,6 +66,8 @@ define signext i16 @atomic_load_i16_unordered(i16 *%a) nounwind { ; RV32IA-LABEL: atomic_load_i16_unordered: ; RV32IA: # %bb.0: ; RV32IA-NEXT: lh a0, 0(a0) +; RV32IA-NEXT: slli a0, a0, 16 +; RV32IA-NEXT: srai a0, a0, 16 ; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomic_load_i16_unordered: @@ -79,6 +85,8 @@ define signext i16 @atomic_load_i16_unordered(i16 *%a) nounwind { ; RV64IA-LABEL: atomic_load_i16_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lh a0, 0(a0) +; RV64IA-NEXT: slli a0, a0, 48 +; RV64IA-NEXT: srai a0, a0, 48 ; RV64IA-NEXT: ret %1 = load atomic i16, i16* %a unordered, align 2 ret i16 %1 @@ -114,6 +122,7 @@ define signext i32 @atomic_load_i32_unordered(i32 *%a) nounwind { ; RV64IA-LABEL: atomic_load_i32_unordered: ; RV64IA: # %bb.0: ; RV64IA-NEXT: lw a0, 0(a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = load atomic i32, i32* %a unordered, align 4 ret i32 %1 @@ -2268,6 +2277,7 @@ define signext i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_xchg_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoswap.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw xchg i32* %a, i32 %b monotonic ret i32 %1 @@ -2303,6 +2313,7 @@ define signext i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_add_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoadd.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw add i32* %a, i32 %b monotonic ret i32 %1 @@ -2340,6 +2351,7 @@ define signext i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { ; RV64IA: # %bb.0: ; RV64IA-NEXT: neg a1, a1 ; RV64IA-NEXT: amoadd.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw sub i32* %a, i32 %b monotonic ret i32 %1 @@ -2375,6 +2387,7 @@ define signext i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_and_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoand.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw and i32* %a, i32 %b monotonic ret i32 %1 @@ -2423,7 +2436,7 @@ define signext i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { ; RV64IA-NEXT: sc.w a3, a3, (a0) ; RV64IA-NEXT: bnez a3, .LBB29_1 ; RV64IA-NEXT: # %bb.2: -; RV64IA-NEXT: mv a0, a2 +; RV64IA-NEXT: sext.w a0, a2 ; RV64IA-NEXT: ret %1 = atomicrmw nand i32* %a, i32 %b monotonic ret i32 %1 @@ -2459,6 +2472,7 @@ define signext i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_or_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoor.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw or i32* %a, i32 %b monotonic ret i32 %1 @@ -2494,6 +2508,7 @@ define signext i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_xor_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amoxor.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw xor i32* %a, i32 %b monotonic ret i32 %1 @@ -2584,6 +2599,7 @@ define signext i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_max_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomax.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw max i32* %a, i32 %b monotonic ret i32 %1 @@ -2674,6 +2690,7 @@ define signext i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_min_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomin.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw min i32* %a, i32 %b monotonic ret i32 %1 @@ -2764,6 +2781,7 @@ define signext i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_umax_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amomaxu.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw umax i32* %a, i32 %b monotonic ret i32 %1 @@ -2854,6 +2872,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { ; RV64IA-LABEL: atomicrmw_umin_i32_monotonic: ; RV64IA: # %bb.0: ; RV64IA-NEXT: amominu.w a0, a1, (a0) +; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: ret %1 = atomicrmw umin i32* %a, i32 %b monotonic ret i32 %1