From 8953720f2307a22c444090109086641777adbd79 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sun, 26 Jul 2009 18:55:14 +0000 Subject: [PATCH] Refactor. Get rid of a few more getOpcode() calls. llvm-svn: 77164 --- llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 12 +++++++----- llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 20 ++++++++++++++++---- llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp | 1 + llvm/lib/Target/ARM/Thumb1RegisterInfo.h | 2 ++ llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp | 9 +++++---- llvm/lib/Target/ARM/Thumb2RegisterInfo.h | 18 +++++++++++++----- 6 files changed, 44 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 2405bd03fd08..2bd407ed3b65 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1028,6 +1028,7 @@ unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, int ARMBaseRegisterInfo:: rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, unsigned FrameReg, int Offset) const { unsigned Opcode = MI.getOpcode(); @@ -1039,18 +1040,18 @@ rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, if (Opcode == ARM::INLINEASM) AddrMode = ARMII::AddrMode2; - if (Opcode == getOpcode(ARMII::ADDri)) { + if (Opcode == ADDriOpc) { Offset += MI.getOperand(FrameRegIdx+1).getImm(); if (Offset == 0) { // Turn it into a move. - MI.setDesc(TII.get(getOpcode(ARMII::MOVr))); + MI.setDesc(TII.get(MOVOpc)); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); MI.RemoveOperand(FrameRegIdx+1); return 0; } else if (Offset < 0) { Offset = -Offset; isSub = true; - MI.setDesc(TII.get(getOpcode(ARMII::SUBri))); + MI.setDesc(TII.get(SUBriOpc)); } // Common case: small offset, fits into instruction. @@ -1144,7 +1145,8 @@ rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, } void ARMBaseRegisterInfo:: -eliminateFrameIndex(MachineBasicBlock::iterator II, +eliminateFrameIndexImpl(MachineBasicBlock::iterator II, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, int SPAdj, RegScavenger *RS) const { unsigned i = 0; MachineInstr &MI = *II; @@ -1178,7 +1180,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, } // modify MI as necessary to handle as much of 'Offset' as possible - Offset = rewriteFrameIndex(MI, i, FrameReg, Offset); + Offset = rewriteFrameIndex(MI, i, MOVOpc,ADDriOpc,SUBriOpc, FrameReg, Offset); if (Offset == 0) return; diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h index b725ee60a7b7..59725fe56a12 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -128,14 +128,26 @@ public: // rewrite MI to access 'Offset' bytes from the FP. Return the offset that // could not be handled directly in MI. - virtual int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, - unsigned FrameReg, int Offset) const; - virtual void eliminateFrameIndex(MachineBasicBlock::iterator II, - int SPAdj, RegScavenger *RS = NULL) const; + virtual int + rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, + unsigned FrameReg, int Offset) const; + + virtual void + eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS = NULL) const { + eliminateFrameIndexImpl(II, ARM::MOVr, ARM::ADDri, ARM::SUBri, SPAdj, RS); + } virtual void emitPrologue(MachineFunction &MF) const; virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; +protected: + void + eliminateFrameIndexImpl(MachineBasicBlock::iterator II, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, + int SPAdj, RegScavenger *RS = NULL) const; + private: unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const; diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp index bf721a5e998f..17949bddeb29 100644 --- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -388,6 +388,7 @@ static void removeOperands(MachineInstr &MI, unsigned i) { int Thumb1RegisterInfo:: rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, unsigned FrameReg, int Offset) const { // if/when eliminateFrameIndex() conforms with ARMBaseRegisterInfo diff --git a/llvm/lib/Target/ARM/Thumb1RegisterInfo.h b/llvm/lib/Target/ARM/Thumb1RegisterInfo.h index 2832a5bc07ce..ab01a264d3bc 100644 --- a/llvm/lib/Target/ARM/Thumb1RegisterInfo.h +++ b/llvm/lib/Target/ARM/Thumb1RegisterInfo.h @@ -51,7 +51,9 @@ public: // rewrite MI to access 'Offset' bytes from the FP. Return the offset that // could not be handled directly in MI. int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, unsigned FrameReg, int Offset) const; + void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS = NULL) const; diff --git a/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp b/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp index ce495fae1cbb..ae2d21e90cdf 100644 --- a/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2RegisterInfo.cpp @@ -165,6 +165,7 @@ requiresRegisterScavenging(const MachineFunction &MF) const { int Thumb2RegisterInfo:: rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, unsigned FrameReg, int Offset) const { unsigned Opcode = MI.getOpcode(); @@ -176,18 +177,18 @@ rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, if (Opcode == ARM::INLINEASM) AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2? - if (Opcode == getOpcode(ARMII::ADDri)) { + if (Opcode == ADDriOpc) { Offset += MI.getOperand(FrameRegIdx+1).getImm(); if (Offset == 0) { // Turn it into a move. - MI.setDesc(TII.get(ARM::t2MOVr)); + MI.setDesc(TII.get(MOVOpc)); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); MI.RemoveOperand(FrameRegIdx+1); return 0; } else if (Offset < 0) { Offset = -Offset; isSub = true; - MI.setDesc(TII.get(getOpcode(ARMII::SUBri))); + MI.setDesc(TII.get(SUBriOpc)); } // Common case: small offset, fits into instruction. @@ -231,7 +232,7 @@ rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, if ((AddrMode != ARMII::AddrModeT2_i8) && (AddrMode != ARMII::AddrModeT2_i12)) { return ARMBaseRegisterInfo::rewriteFrameIndex(MI, FrameRegIdx, - FrameReg, Offset); + ARM::t2MOVr, ARM::t2ADDri, ARM::t2SUBri, FrameReg, Offset); } unsigned NumBits = 0; diff --git a/llvm/lib/Target/ARM/Thumb2RegisterInfo.h b/llvm/lib/Target/ARM/Thumb2RegisterInfo.h index 57c066327759..72a1cd1c8067 100644 --- a/llvm/lib/Target/ARM/Thumb2RegisterInfo.h +++ b/llvm/lib/Target/ARM/Thumb2RegisterInfo.h @@ -27,11 +27,6 @@ struct Thumb2RegisterInfo : public ARMBaseRegisterInfo { public: Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI); - // rewrite MI to access 'Offset' bytes from the FP. Return the offset that - // could not be handled directly in MI. - int rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, - unsigned FrameReg, int Offset) const; - /// emitLoadConstPool - Emits a load from constpool to materialize the /// specified immediate. void emitLoadConstPool(MachineBasicBlock &MBB, @@ -42,6 +37,19 @@ public: unsigned PredReg = 0) const; bool requiresRegisterScavenging(const MachineFunction &MF) const; + + // rewrite MI to access 'Offset' bytes from the FP. Return the offset that + // could not be handled directly in MI. + virtual int + rewriteFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, + unsigned MOVOpc, unsigned ADDriOpc, unsigned SUBriOpc, + unsigned FrameReg, int Offset) const; + + void eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS = NULL) const { + ARMBaseRegisterInfo::eliminateFrameIndexImpl(II, ARM::t2MOVr, ARM::t2ADDri, + ARM::t2SUBri, SPAdj, RS); + } }; }