forked from OSchip/llvm-project
parent
fd9c89e84b
commit
892f54f408
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@ -11,8 +11,10 @@ LIBRARYNAME = LLVMHexagonCodeGen
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TARGET = Hexagon
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# Make sure that tblgen is run, first thing.
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BUILT_SOURCES = HexagonGenRegisterInfo.inc \
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BUILT_SOURCES = HexagonGen.inc \
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HexagonGenRegisterInfo.inc \
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HexagonGenInstrInfo.inc \
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HexagonGenAsmMatcher.inc \
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HexagonGenAsmWriter.inc \
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HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \
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HexagonGenCallingConv.inc \
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@ -20,6 +22,6 @@ BUILT_SOURCES = HexagonGenRegisterInfo.inc \
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HexagonGenMCCodeEmitter.inc \
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HexagonGenDisassemblerTables.inc
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DIRS = TargetInfo MCTargetDesc Disassembler
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DIRS = TargetInfo MCTargetDesc Disassembler AsmParser
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include $(LEVEL)/Makefile.common
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