forked from OSchip/llvm-project
[x86] add tests for vector select; NFC
This commit is contained in:
Sanjay Patel
parent
05f64b5ac9
commit
8918814032
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@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; PR28925
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@ -169,3 +169,239 @@ define <2 x double> @vsel_nonzero_constants(<2 x double> %x, <2 x double> %y) {
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ret <2 x double> %r
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}
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define <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {
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; SSE-LABEL: signbit_mask_v16i8:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pcmpgtb %xmm0, %xmm2
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; SSE-NEXT: pand %xmm1, %xmm2
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: signbit_mask_v16i8:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp slt <16 x i8> %a, zeroinitializer
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%r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer
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ret <16 x i8> %r
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}
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define <8 x i16> @signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; SSE-LABEL: signbit_mask_v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pcmpgtw %xmm0, %xmm2
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; SSE-NEXT: pand %xmm1, %xmm2
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: signbit_mask_v8i16:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpcmpgtw %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp slt <8 x i16> %a, zeroinitializer
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%r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer
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ret <8 x i16> %r
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}
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define <4 x i32> @signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; SSE-LABEL: signbit_mask_v4i32:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pcmpgtd %xmm0, %xmm2
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; SSE-NEXT: pand %xmm1, %xmm2
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: signbit_mask_v4i32:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpcmpgtd %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp slt <4 x i32> %a, zeroinitializer
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%r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer
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ret <4 x i32> %r
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}
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define <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; SSE2-LABEL: signbit_mask_v2i64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; SSE2-NEXT: pxor %xmm0, %xmm0
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; SSE2-NEXT: pcmpgtd %xmm2, %xmm0
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; SSE2-NEXT: pand %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE42-LABEL: signbit_mask_v2i64:
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; SSE42: # %bb.0:
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; SSE42-NEXT: pxor %xmm2, %xmm2
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; SSE42-NEXT: pcmpgtq %xmm0, %xmm2
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; SSE42-NEXT: pand %xmm1, %xmm2
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; SSE42-NEXT: movdqa %xmm2, %xmm0
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: signbit_mask_v2i64:
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; AVX: # %bb.0:
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; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0
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; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = icmp slt <2 x i64> %a, zeroinitializer
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%r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer
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ret <2 x i64> %r
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}
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define <32 x i8> @signbit_mask_v32i8(<32 x i8> %a, <32 x i8> %b) {
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; SSE-LABEL: signbit_mask_v32i8:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm4, %xmm4
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; SSE-NEXT: pxor %xmm5, %xmm5
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; SSE-NEXT: pcmpgtb %xmm1, %xmm5
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; SSE-NEXT: pcmpgtb %xmm0, %xmm4
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; SSE-NEXT: pand %xmm2, %xmm4
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; SSE-NEXT: pand %xmm3, %xmm5
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; SSE-NEXT: movdqa %xmm4, %xmm0
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; SSE-NEXT: movdqa %xmm5, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: signbit_mask_v32i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtb %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: signbit_mask_v32i8:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%cond = icmp slt <32 x i8> %a, zeroinitializer
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%r = select <32 x i1> %cond, <32 x i8> %b, <32 x i8> zeroinitializer
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ret <32 x i8> %r
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}
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define <16 x i16> @signbit_mask_v16i16(<16 x i16> %a, <16 x i16> %b) {
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; SSE-LABEL: signbit_mask_v16i16:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm4, %xmm4
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; SSE-NEXT: pxor %xmm5, %xmm5
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; SSE-NEXT: pcmpgtw %xmm1, %xmm5
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; SSE-NEXT: pcmpgtw %xmm0, %xmm4
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; SSE-NEXT: pand %xmm2, %xmm4
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; SSE-NEXT: pand %xmm3, %xmm5
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; SSE-NEXT: movdqa %xmm4, %xmm0
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; SSE-NEXT: movdqa %xmm5, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: signbit_mask_v16i16:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtw %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: signbit_mask_v16i16:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpcmpgtw %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%cond = icmp slt <16 x i16> %a, zeroinitializer
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%r = select <16 x i1> %cond, <16 x i16> %b, <16 x i16> zeroinitializer
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ret <16 x i16> %r
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}
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define <8 x i32> @signbit_mask_v8i32(<8 x i32> %a, <8 x i32> %b) {
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; SSE-LABEL: signbit_mask_v8i32:
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; SSE: # %bb.0:
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; SSE-NEXT: pxor %xmm4, %xmm4
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; SSE-NEXT: pxor %xmm5, %xmm5
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; SSE-NEXT: pcmpgtd %xmm1, %xmm5
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; SSE-NEXT: pcmpgtd %xmm0, %xmm4
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; SSE-NEXT: pand %xmm2, %xmm4
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; SSE-NEXT: pand %xmm3, %xmm5
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; SSE-NEXT: movdqa %xmm4, %xmm0
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; SSE-NEXT: movdqa %xmm5, %xmm1
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: signbit_mask_v8i32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpgtd %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtd %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: signbit_mask_v8i32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpcmpgtd %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%cond = icmp slt <8 x i32> %a, zeroinitializer
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%r = select <8 x i1> %cond, <8 x i32> %b, <8 x i32> zeroinitializer
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ret <8 x i32> %r
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}
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define <4 x i64> @signbit_mask_v4i64(<4 x i64> %a, <4 x i64> %b) {
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; SSE2-LABEL: signbit_mask_v4i64:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
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; SSE2-NEXT: pxor %xmm4, %xmm4
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpgtd %xmm5, %xmm1
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; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm4
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; SSE2-NEXT: pand %xmm2, %xmm4
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; SSE2-NEXT: pand %xmm3, %xmm1
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; SSE2-NEXT: movdqa %xmm4, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE42-LABEL: signbit_mask_v4i64:
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; SSE42: # %bb.0:
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; SSE42-NEXT: pxor %xmm4, %xmm4
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; SSE42-NEXT: pxor %xmm5, %xmm5
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; SSE42-NEXT: pcmpgtq %xmm1, %xmm5
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; SSE42-NEXT: pcmpgtq %xmm0, %xmm4
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; SSE42-NEXT: pand %xmm2, %xmm4
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; SSE42-NEXT: pand %xmm3, %xmm5
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; SSE42-NEXT: movdqa %xmm4, %xmm0
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; SSE42-NEXT: movdqa %xmm5, %xmm1
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; SSE42-NEXT: retq
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;
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; AVX1-LABEL: signbit_mask_v4i64:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: signbit_mask_v4i64:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm0
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; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX2-NEXT: retq
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%cond = icmp slt <4 x i64> %a, zeroinitializer
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%r = select <4 x i1> %cond, <4 x i64> %b, <4 x i64> zeroinitializer
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ret <4 x i64> %r
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}
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