forked from OSchip/llvm-project
[AArch64] Allow pairing lr with other GPRs for WinCFI
This saves one instruction per prologue/epilogue for any function with an odd number of callee-saved GPRs, but more importantly, allows such functions to match the packed unwind format. Differential Revision: https://reviews.llvm.org/D88699
This commit is contained in:
Martin Storsjö
parent
3780a4e568
commit
890af2f003
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@ -1314,6 +1314,14 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
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return;
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case AArch64::SEH_SaveRegP:
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if (MI->getOperand(1).getImm() == 30 && MI->getOperand(0).getImm() >= 19 &&
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MI->getOperand(0).getImm() <= 28) {
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assert((MI->getOperand(0).getImm() - 19) % 2 == 0 &&
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"Register paired with LR must be odd");
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TS->EmitARM64WinCFISaveLRPair(MI->getOperand(0).getImm(),
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MI->getOperand(2).getImm());
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return;
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}
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assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
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"Non-consecutive registers not allowed for save_regp");
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TS->EmitARM64WinCFISaveRegP(MI->getOperand(0).getImm(),
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@ -1988,21 +1988,28 @@ static bool produceCompactUnwindFrame(MachineFunction &MF) {
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}
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static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
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bool NeedsWinCFI) {
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bool NeedsWinCFI, bool IsFirst) {
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// If we are generating register pairs for a Windows function that requires
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// EH support, then pair consecutive registers only. There are no unwind
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// opcodes for saves/restores of non-consectuve register pairs.
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// The unwind opcodes are save_regp, save_regp_x, save_fregp, save_frepg_x.
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// The unwind opcodes are save_regp, save_regp_x, save_fregp, save_frepg_x,
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// save_lrpair.
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// https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
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// TODO: LR can be paired with any register. We don't support this yet in
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// the MCLayer. We need to add support for the save_lrpair unwind code.
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if (Reg2 == AArch64::FP)
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return true;
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if (!NeedsWinCFI)
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return false;
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if (Reg2 == Reg1 + 1)
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return false;
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// If pairing a GPR with LR, the pair can be described by the save_lrpair
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// opcode. If this is the first register pair, it would end up with a
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// predecrement, but there's no save_lrpair_x opcode, so we can only do this
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// if LR is paired with something else than the first register.
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// The save_lrpair opcode requires the first register to be an odd one.
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if (Reg1 >= AArch64::X19 && Reg1 <= AArch64::X27 &&
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(Reg1 - AArch64::X19) % 2 == 0 && Reg2 == AArch64::LR && !IsFirst)
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return false;
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return true;
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}
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@ -2011,9 +2018,10 @@ static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2,
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/// LR and FP need to be allocated together when the frame needs to save
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/// the frame-record. This means any other register pairing with LR is invalid.
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static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2,
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bool UsesWinAAPCS, bool NeedsWinCFI, bool NeedsFrameRecord) {
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bool UsesWinAAPCS, bool NeedsWinCFI,
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bool NeedsFrameRecord, bool IsFirst) {
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if (UsesWinAAPCS)
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return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI);
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return invalidateWindowsRegisterPairing(Reg1, Reg2, NeedsWinCFI, IsFirst);
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// If we need to store the frame record, don't pair any register
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// with LR other than FP.
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@ -2112,16 +2120,18 @@ static void computeCalleeSaveRegisterPairs(
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// Add the next reg to the pair if it is in the same register class.
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if (unsigned(i + RegInc) < Count) {
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unsigned NextReg = CSI[i + RegInc].getReg();
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bool IsFirst = i == FirstReg;
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switch (RPI.Type) {
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case RegPairInfo::GPR:
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if (AArch64::GPR64RegClass.contains(NextReg) &&
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!invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows, NeedsWinCFI,
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NeedsFrameRecord))
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!invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows,
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NeedsWinCFI, NeedsFrameRecord, IsFirst))
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RPI.Reg2 = NextReg;
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break;
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case RegPairInfo::FPR64:
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if (AArch64::FPR64RegClass.contains(NextReg) &&
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!invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI))
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!invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI,
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IsFirst))
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RPI.Reg2 = NextReg;
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break;
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case RegPairInfo::FPR128:
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@ -213,8 +213,7 @@ declare void @llvm.stackrestore(i8*)
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; CHECK-LABEL: snprintf
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; CHECK-DAG: sub sp, sp, #96
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; CHECK-DAG: stp x19, x20, [sp, #16]
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; CHECK-DAG: str x21, [sp, #32]
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; CHECK-DAG: str x30, [sp, #40]
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; CHECK-DAG: stp x21, x30, [sp, #32]
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; CHECK-DAG: add x8, sp, #56
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; CHECK-DAG: mov x19, x2
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; CHECK-DAG: mov x20, x1
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@ -232,8 +231,7 @@ declare void @llvm.stackrestore(i8*)
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; CHECK-DAG: mov x3, x19
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; CHECK-DAG: mov x4, xzr
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; CHECK-DAG: bl __stdio_common_vsprintf
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; CHECK-DAG: ldr x30, [sp, #40]
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; CHECK-DAG: ldr x21, [sp, #32]
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; CHECK-DAG: ldp x21, x30, [sp, #32]
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; CHECK-DAG: ldp x19, x20, [sp, #16]
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; CHECK-DAG: cmp w0, #0
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; CHECK-DAG: csinv w0, w0, wzr, ge
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@ -0,0 +1,74 @@
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# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
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# RUN: -stop-after=prologepilog | FileCheck %s
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# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
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# RUN: | FileCheck --check-prefix=ASM %s
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# Check that an odd callee-saved GPR is paired with lr
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# CHECK: early-clobber $sp = frame-setup STPXpre killed $x19, killed $x20, $sp, -4
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# CHECK-NEXT: frame-setup SEH_SaveRegP_X 19, 20, -32
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# CHECK-NEXT: frame-setup STPXi killed $x21, killed $lr, $sp, 2
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# CHECK-NEXT: frame-setup SEH_SaveRegP 21, 30, 16
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# CHECK-NEXT: frame-setup SEH_PrologEnd
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# ASM: stp x19, x20, [sp, #-32]!
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# ASM-NEXT: .seh_save_regp_x x19, 32
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# ASM-NEXT: stp x21, x30, [sp, #16]
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# ASM-NEXT: .seh_save_lrpair x21, 16
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# ASM-NEXT: .seh_endprologue
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--- |
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define dso_local i32 @func(i32 %a) { ret i32 %a }
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declare dso_local i32 @other()
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...
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---
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name: func
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 4
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x21, $x19, $x20
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BL @other, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
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$x19 = ADDXrr $x0, $x0
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$x20 = ADDXrr $x19, $x0
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$x21 = ADDXrr $x20, killed $x19
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$x0 = ADDXrr $x0, killed $x21
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RET_ReallyLR
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...
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@ -0,0 +1,65 @@
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# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
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# RUN: -stop-after=prologepilog | FileCheck %s
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# Check that lr isn't paired with a GPR if it's the first pair, as
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# that can't be described as a SEH opcode if combined with predecrement.
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# CHECK: early-clobber $sp = frame-setup STRXpre killed $x19, $sp, -16
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# CHECK-NEXT: frame-setup SEH_SaveReg_X 19, -16
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# CHECK-NEXT: frame-setup STRXui killed $lr, $sp, 1
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# CHECK-NEXT: frame-setup SEH_SaveReg 30, 8
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# CHECK-NEXT: frame-setup SEH_PrologEnd
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--- |
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define dso_local i32 @func(i32 %a) { ret i32 %a }
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declare dso_local i32 @other()
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...
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---
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name: func
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 4
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x19
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BL @other, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
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$x19 = ADDXrr $x0, $x0
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$x0 = ADDXrr $x0, killed $x19
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RET_ReallyLR
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...
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@ -0,0 +1,68 @@
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# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
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# RUN: -stop-after=prologepilog | FileCheck %s
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# Check that an unpaired register that is even isn't paired with lr.
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# CHECK: early-clobber $sp = frame-setup STPXpre killed $x19, killed $x20, $sp, -4
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# CHECK-NEXT: frame-setup SEH_SaveRegP_X 19, 20, -32
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# CHECK-NEXT: frame-setup STRXui killed $x22, $sp, 2
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# CHECK-NEXT: frame-setup SEH_SaveReg 22, 16
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# CHECK-NEXT: frame-setup STRXui killed $lr, $sp, 3
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# CHECK-NEXT: frame-setup SEH_SaveReg 30, 24
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# CHECK-NEXT: frame-setup SEH_PrologEnd
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--- |
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define dso_local i32 @func(i32 %a) { ret i32 %a }
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declare dso_local i32 @other()
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...
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---
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name: func
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 4
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x22, $x19, $x20
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BL @other, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
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$x19 = ADDXrr $x0, $x0
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$x20 = ADDXrr $x19, $x0
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$x22 = ADDXrr $x20, killed $x19
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$x0 = ADDXrr $x0, killed $x22
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RET_ReallyLR
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...
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