forked from OSchip/llvm-project
[X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries (PR37093)
llvm-svn: 329912
This commit is contained in:
Simon Pilgrim
parent
c645f61ada
commit
8904a86f65
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@ -4267,13 +4267,12 @@ let SchedRW = [WriteVecLoad] in {
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}
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multiclass avx512_movnt<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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PatFrag st_frag = alignednontemporalstore,
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InstrItinClass itin = IIC_SSE_MOVNT> {
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PatFrag st_frag = alignednontemporalstore> {
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let SchedRW = [WriteVecStore], AddedComplexity = 400 in
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def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(st_frag (_.VT _.RC:$src), addr:$dst)],
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_.ExeDomain, itin>, EVEX, EVEX_CD8<_.EltSize, CD8VF>;
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_.ExeDomain>, EVEX, EVEX_CD8<_.EltSize, CD8VF>;
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}
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multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr,
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@ -717,13 +717,13 @@ class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
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// SS42FI - SSE 4.2 instructions with T8XD prefix.
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// NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
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class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8XD, Requires<[HasSSE42]>;
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// SS42AI = SSE 4.2 instructions with TA prefix
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class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, NoItinerary, SSEPackedInt>, TAPD,
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Requires<[UseSSE42]>;
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// AVX Instruction Templates:
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@ -857,19 +857,19 @@ class AVX512<bits<8> o, Format F, dag outs, dag ins, string asm,
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// AES8I
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// These use the same encoding as the SSE4.2 T8 and TA encodings.
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class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = IIC_AES>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD,
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list<dag>pattern>
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: I<o, F, outs, ins, asm, pattern, NoItinerary, SSEPackedInt>, T8PD,
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Requires<[NoAVX, HasAES]>;
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class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern, NoItinerary, SSEPackedInt>, TAPD,
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Requires<[NoAVX, HasAES]>;
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// PCLMUL Instruction Templates
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class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TAPD;
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list<dag>pattern>
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: Ii8<o, F, outs, ins, asm, pattern, NoItinerary, SSEPackedInt>, TAPD;
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// FMA3 Instruction Templates
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class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
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@ -3384,27 +3384,23 @@ def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
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(ins f128mem:$dst, VR128:$src),
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"movntps\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v4f32 VR128:$src),
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addr:$dst)],
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IIC_SSE_MOVNT>, VEX, VEX_WIG;
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addr:$dst)]>, VEX, VEX_WIG;
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def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
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(ins f128mem:$dst, VR128:$src),
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"movntpd\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v2f64 VR128:$src),
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addr:$dst)],
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IIC_SSE_MOVNT>, VEX, VEX_WIG;
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addr:$dst)]>, VEX, VEX_WIG;
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def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
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(ins f256mem:$dst, VR256:$src),
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"movntps\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v8f32 VR256:$src),
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addr:$dst)],
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IIC_SSE_MOVNT>, VEX, VEX_L, VEX_WIG;
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addr:$dst)]>, VEX, VEX_L, VEX_WIG;
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def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
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(ins f256mem:$dst, VR256:$src),
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"movntpd\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v4f64 VR256:$src),
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addr:$dst)],
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IIC_SSE_MOVNT>, VEX, VEX_L, VEX_WIG;
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addr:$dst)]>, VEX, VEX_L, VEX_WIG;
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} // SchedRW
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let ExeDomain = SSEPackedInt, SchedRW = [WriteVecStore] in {
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@ -3412,45 +3408,38 @@ def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
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(ins i128mem:$dst, VR128:$src),
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"movntdq\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v2i64 VR128:$src),
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addr:$dst)],
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IIC_SSE_MOVNT>, VEX, VEX_WIG;
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addr:$dst)]>, VEX, VEX_WIG;
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def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
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(ins i256mem:$dst, VR256:$src),
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"movntdq\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v4i64 VR256:$src),
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addr:$dst)],
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IIC_SSE_MOVNT>, VEX, VEX_L, VEX_WIG;
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addr:$dst)]>, VEX, VEX_L, VEX_WIG;
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} // ExeDomain, SchedRW
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} // Predicates
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let SchedRW = [WriteVecStore] in {
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def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntps\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
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IIC_SSE_MOVNT>;
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[(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
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def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntpd\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
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IIC_SSE_MOVNT>;
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[(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
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} // SchedRW
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let ExeDomain = SSEPackedInt, SchedRW = [WriteVecStore] in
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def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
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"movntdq\t{$src, $dst|$dst, $src}",
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[(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
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IIC_SSE_MOVNT>;
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[(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>;
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let SchedRW = [WriteStore] in {
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// There is no AVX form for instructions below this point
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def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"movnti{l}\t{$src, $dst|$dst, $src}",
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[(nontemporalstore (i32 GR32:$src), addr:$dst)],
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IIC_SSE_MOVNT>,
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[(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
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PS, Requires<[HasSSE2]>;
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def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"movnti{q}\t{$src, $dst|$dst, $src}",
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[(nontemporalstore (i64 GR64:$src), addr:$dst)],
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IIC_SSE_MOVNT>,
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[(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
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PS, Requires<[HasSSE2]>;
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} // SchedRW = [WriteStore]
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@ -4820,17 +4809,16 @@ let SchedRW = [WriteVecLoad] in {
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let Predicates = [HasAVX] in {
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def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"vlddqu\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
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IIC_SSE_LDDQU>, VEX, VEX_WIG;
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[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>,
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VEX, VEX_WIG;
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def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
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"vlddqu\t{$src, $dst|$dst, $src}",
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[(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))],
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IIC_SSE_LDDQU>, VEX, VEX_L, VEX_WIG;
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[(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
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VEX, VEX_L, VEX_WIG;
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} // Predicates
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def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"lddqu\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
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IIC_SSE_LDDQU>;
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[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
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} // SchedRW
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//===---------------------------------------------------------------------===//
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@ -6220,35 +6208,33 @@ defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
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let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
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def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"popcnt{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
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IIC_SSE_POPCNT_RR>, Sched<[WritePOPCNT]>,
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OpSize16, XS;
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[(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
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Sched<[WritePOPCNT]>, OpSize16, XS;
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def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"popcnt{w}\t{$src, $dst|$dst, $src}",
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[(set GR16:$dst, (ctpop (loadi16 addr:$src))),
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(implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
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(implicit EFLAGS)]>,
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Sched<[WritePOPCNTLd]>, OpSize16, XS;
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def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"popcnt{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
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IIC_SSE_POPCNT_RR>, Sched<[WritePOPCNT]>,
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OpSize32, XS;
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[(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
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Sched<[WritePOPCNT]>, OpSize32, XS;
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def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"popcnt{l}\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (ctpop (loadi32 addr:$src))),
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(implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
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(implicit EFLAGS)]>,
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Sched<[WritePOPCNTLd]>, OpSize32, XS;
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def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
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IIC_SSE_POPCNT_RR>, Sched<[WritePOPCNT]>, XS;
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[(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
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Sched<[WritePOPCNT]>, XS;
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def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"popcnt{q}\t{$src, $dst|$dst, $src}",
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[(set GR64:$dst, (ctpop (loadi64 addr:$src))),
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(implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
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(implicit EFLAGS)]>,
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Sched<[WritePOPCNTLd]>, XS;
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}
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@ -7072,15 +7058,15 @@ class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
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RegisterClass RCIn, SDPatternOperator Int> :
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SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
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!strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
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[(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
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[(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))]>,
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Sched<[WriteCRC32]>;
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class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
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X86MemOperand x86memop, SDPatternOperator Int> :
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SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
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!strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
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[(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
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IIC_CRC32_MEM>, Sched<[WriteCRC32Ld, ReadAfterLd]>;
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[(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))]>,
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Sched<[WriteCRC32Ld, ReadAfterLd]>;
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let Constraints = "$src1 = $dst" in {
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def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
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@ -7114,7 +7100,7 @@ let Constraints = "$src1 = $dst" in {
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// FIXME: Is there a better scheduler itinerary for SHA than WriteVecIMul?
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multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
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OpndItins itins, bit UsesXMM0 = 0> {
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X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
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def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!if(UsesXMM0,
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@ -7122,8 +7108,8 @@ multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
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[!if(UsesXMM0,
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))], itins.rr>,
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T8, Sched<[itins.Sched]>;
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(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
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T8, Sched<[sched]>;
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def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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@ -7134,8 +7120,8 @@ multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
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(set VR128:$dst, (IntId VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
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(set VR128:$dst, (IntId VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)))))], itins.rm>, T8,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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(bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8,
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Sched<[sched.Folded, ReadAfterLd]>;
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}
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let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
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@ -7153,23 +7139,23 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
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(int_x86_sha1rnds4 VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2)),
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(i8 imm:$src3)))], IIC_SSE_INTMUL_P_RM>, TA,
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Sched<[WriteVecIMulLd, ReadAfterLd]>;
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Sched<[WriteVecIMul.Folded, ReadAfterLd]>;
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defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte,
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SSE_INTMUL_ITINS_P>;
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WriteVecIMul>;
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defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1,
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SSE_INTMUL_ITINS_P>;
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WriteVecIMul>;
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defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2,
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SSE_INTMUL_ITINS_P>;
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WriteVecIMul>;
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let Uses=[XMM0] in
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defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
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SSE_INTMUL_ITINS_P, 1>;
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WriteVecIMul, 1>;
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defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
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SSE_INTMUL_ITINS_P>;
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WriteVecIMul>;
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defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2,
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SSE_INTMUL_ITINS_P>;
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WriteVecIMul>;
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}
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// Aliases with explicit %xmm0
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@ -7309,16 +7295,16 @@ let Predicates = [NoAVX, HasPCLMUL] in {
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(ins VR128:$src1, VR128:$src2, u8imm:$src3),
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"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
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[(set VR128:$dst,
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(int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
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IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
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(int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
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Sched<[WriteCLMul]>;
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def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
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"pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set VR128:$dst,
|
||||
(int_x86_pclmulqdq VR128:$src1, (memopv2i64 addr:$src2),
|
||||
imm:$src3))],
|
||||
IIC_SSE_PCLMULQDQ_RM>, Sched<[WriteCLMulLd, ReadAfterLd]>;
|
||||
imm:$src3))]>,
|
||||
Sched<[WriteCLMulLd, ReadAfterLd]>;
|
||||
} // Constraints = "$src1 = $dst"
|
||||
|
||||
def : Pat<(int_x86_pclmulqdq (memopv2i64 addr:$src2), VR128:$src1,
|
||||
|
|
@ -7346,15 +7332,15 @@ multiclass vpclmulqdq<RegisterClass RC, X86MemOperand MemOp,
|
|||
(ins RC:$src1, RC:$src2, u8imm:$src3),
|
||||
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
|
||||
[(set RC:$dst,
|
||||
(IntId RC:$src1, RC:$src2, imm:$src3))], IIC_SSE_PCLMULQDQ_RR>,
|
||||
(IntId RC:$src1, RC:$src2, imm:$src3))]>,
|
||||
Sched<[WriteCLMul]>;
|
||||
|
||||
def rm : PCLMULIi8<0x44, MRMSrcMem, (outs RC:$dst),
|
||||
(ins RC:$src1, MemOp:$src2, u8imm:$src3),
|
||||
"vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
|
||||
[(set RC:$dst,
|
||||
(IntId RC:$src1, (LdFrag addr:$src2), imm:$src3))],
|
||||
IIC_SSE_PCLMULQDQ_RM>, Sched<[WriteCLMulLd, ReadAfterLd]>;
|
||||
(IntId RC:$src1, (LdFrag addr:$src2), imm:$src3))]>,
|
||||
Sched<[WriteCLMulLd, ReadAfterLd]>;
|
||||
|
||||
// We can commute a load in the first operand by swapping the sources and
|
||||
// rotating the immediate.
|
||||
|
|
@ -7433,10 +7419,10 @@ def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
|
|||
let AddedComplexity = 400 in { // Prefer non-temporal versions
|
||||
let hasSideEffects = 0, mayStore = 1, SchedRW = [WriteStore] in {
|
||||
def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
|
||||
"movntss\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVNT>, XS;
|
||||
"movntss\t{$src, $dst|$dst, $src}", []>, XS;
|
||||
|
||||
def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
||||
"movntsd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVNT>, XD;
|
||||
"movntsd\t{$src, $dst|$dst, $src}", []>, XD;
|
||||
} // SchedRW
|
||||
|
||||
def : Pat<(nontemporalstore FR32:$src, addr:$dst),
|
||||
|
|
@ -7737,6 +7723,7 @@ let ExeDomain = SSEPackedDouble in {
|
|||
//===----------------------------------------------------------------------===//
|
||||
// VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
|
||||
//
|
||||
|
||||
let ExeDomain = SSEPackedSingle in {
|
||||
let isCommutable = 1 in
|
||||
def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
|
||||
|
|
@ -7779,26 +7766,28 @@ def : Pat<(v4i64 (X86VPerm2x128 (loadv4i64 addr:$src2),
|
|||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// VZERO - Zero YMM registers
|
||||
// Note: These instruction do not affect the YMM16-YMM31.
|
||||
//
|
||||
// Note, these instruction do not affect the YMM16-YMM31.
|
||||
|
||||
let SchedRW = [WriteSystem] in {
|
||||
let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
|
||||
YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
|
||||
// Zero All YMM registers
|
||||
def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
|
||||
[(int_x86_avx_vzeroall)], IIC_AVX_ZERO>, PS, VEX, VEX_L,
|
||||
[(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L,
|
||||
Requires<[HasAVX]>, VEX_WIG;
|
||||
|
||||
// Zero Upper bits of YMM registers
|
||||
def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
|
||||
[(int_x86_avx_vzeroupper)], IIC_AVX_ZERO>, PS, VEX,
|
||||
[(int_x86_avx_vzeroupper)]>, PS, VEX,
|
||||
Requires<[HasAVX]>, VEX_WIG;
|
||||
} // Defs
|
||||
} // SchedRW
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Half precision conversion instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
|
||||
multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop> {
|
||||
def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
|
||||
"vcvtph2ps\t{$src, $dst|$dst, $src}",
|
||||
|
|
|
|||
|
|
@ -254,9 +254,6 @@ def IIC_MOVZX : InstrItinClass;
|
|||
def IIC_MOVZX_R16_R8 : InstrItinClass;
|
||||
def IIC_MOVZX_R16_M8 : InstrItinClass;
|
||||
|
||||
def IIC_REP_MOVS : InstrItinClass;
|
||||
def IIC_REP_STOS : InstrItinClass;
|
||||
|
||||
// SSE scalar/parallel binary operations
|
||||
def IIC_SSE_ALU_F32S_RR : InstrItinClass;
|
||||
def IIC_SSE_ALU_F32S_RM : InstrItinClass;
|
||||
|
|
@ -359,10 +356,6 @@ def IIC_SSE_MOVQ_RR : InstrItinClass;
|
|||
|
||||
def IIC_SSE_MOV_LH : InstrItinClass;
|
||||
|
||||
def IIC_SSE_LDDQU : InstrItinClass;
|
||||
|
||||
def IIC_SSE_MOVNT : InstrItinClass;
|
||||
|
||||
def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
|
||||
def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
|
||||
def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
|
||||
|
|
@ -391,14 +384,7 @@ def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
|
|||
def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
|
||||
def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
|
||||
|
||||
def IIC_AVX_ZERO : InstrItinClass;
|
||||
|
||||
def IIC_AES : InstrItinClass;
|
||||
def IIC_BLEND_MEM : InstrItinClass;
|
||||
def IIC_BLEND_NOMEM : InstrItinClass;
|
||||
def IIC_CBW : InstrItinClass;
|
||||
def IIC_CRC32_REG : InstrItinClass;
|
||||
def IIC_CRC32_MEM : InstrItinClass;
|
||||
def IIC_SSE_DPPD_RR : InstrItinClass;
|
||||
def IIC_SSE_DPPD_RM : InstrItinClass;
|
||||
def IIC_SSE_DPPS_RR : InstrItinClass;
|
||||
|
|
@ -415,10 +401,6 @@ def IIC_SSE_ROUNDPS_REG : InstrItinClass;
|
|||
def IIC_SSE_ROUNDPS_MEM : InstrItinClass;
|
||||
def IIC_SSE_ROUNDPD_REG : InstrItinClass;
|
||||
def IIC_SSE_ROUNDPD_MEM : InstrItinClass;
|
||||
def IIC_SSE_POPCNT_RR : InstrItinClass;
|
||||
def IIC_SSE_POPCNT_RM : InstrItinClass;
|
||||
def IIC_SSE_PCLMULQDQ_RR : InstrItinClass;
|
||||
def IIC_SSE_PCLMULQDQ_RM : InstrItinClass;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Processor instruction itineraries.
|
||||
|
|
|
|||
Loading…
Reference in New Issue